| Resume alert | Resumes 201 - 210 of 514 |
Electrical Engineer Power Plant
Fremont, CA
... Tools: Packet tracer, ModelSim, X-Manager, Putty, MATLAB, EDA, Vivado, Wire shark, Cadence, EDUCATION: Northwestern Polytechnic University, Fremont, CA. (May 2017) Masters in Electrical Engineer Course Information System Analysis and Simulation, ... - 2017 Mar 14
... Tools: Packet tracer, ModelSim, X-Manager, Putty, MATLAB, EDA, Vivado, Wire shark, Cadence, EDUCATION: Northwestern Polytechnic University, Fremont, CA. (May 2017) Masters in Electrical Engineer Course Information System Analysis and Simulation, ... - 2017 Mar 14
Actively seeking full time position as a Physical Design Engineer
San Jose, CA
... Bachelor of Engineering, Electronics & Communication, Visvesvaraya Technological University, India July’11 SKILLS CAD(EDA) Tools Synopsys VCS, Cadence Virtuoso IC Design suite, Spectre, IC Compiler, HSpice Skills Synthesis, RTL simulation, Logic ... - 2017 Mar 09
... Bachelor of Engineering, Electronics & Communication, Visvesvaraya Technological University, India July’11 SKILLS CAD(EDA) Tools Synopsys VCS, Cadence Virtuoso IC Design suite, Spectre, IC Compiler, HSpice Skills Synthesis, RTL simulation, Logic ... - 2017 Mar 09
Physical Design Full Time
San Jose, CA
... or related position Core Qualification • Experienced with physical design and complete flow • Experienced with EDA tools: Cadence Virtuoso, DC, IC Compiler, PrimeTime, Verdi, VCS, DVE, ModelSim, etc • Experienced with Verilog, SystemVerilog, VHDL, ... - 2017 Mar 02
... or related position Core Qualification • Experienced with physical design and complete flow • Experienced with EDA tools: Cadence Virtuoso, DC, IC Compiler, PrimeTime, Verdi, VCS, DVE, ModelSim, etc • Experienced with Verilog, SystemVerilog, VHDL, ... - 2017 Mar 02
Design Electrical Engineering
Sunnyvale, CA
... and Communication 09/2007 – 06/2011 PES Institute of Technology, Bengaluru, India GPA: 8.12/10.00 Skill Set Language : C, C++, Verilog, VHDL, System Verilog, Perl, TCL, HSpice Software & IDEs : Cadence – Virtuoso, Encounter, Assura, Quantus RC; ... - 2017 Mar 01
... and Communication 09/2007 – 06/2011 PES Institute of Technology, Bengaluru, India GPA: 8.12/10.00 Skill Set Language : C, C++, Verilog, VHDL, System Verilog, Perl, TCL, HSpice Software & IDEs : Cadence – Virtuoso, Encounter, Assura, Quantus RC; ... - 2017 Mar 01
Design Engineer Technical
Santa Clara, CA
... TECHNICAL SKILLS Tools : Libero SoC, Modelsim, CCS, OrCAD, Matlab, MPLAB, Cadence Virtuoso. Languages : Verilog, Assembly VISA STATUS On H4B VISA with EAD (Work Authorization). - 2017 Mar 01
... TECHNICAL SKILLS Tools : Libero SoC, Modelsim, CCS, OrCAD, Matlab, MPLAB, Cadence Virtuoso. Languages : Verilog, Assembly VISA STATUS On H4B VISA with EAD (Work Authorization). - 2017 Mar 01
Design Electrical Engineering
San Jose, CA
... ARM Processor SKILLS Programming Languages : C, C++,Perl Hardware Languages : Verilog,VHDL,MATLAB EDA Tools : Cadence Virtuoso, Encounter, Design Vision, Prime Time, Xilinx ISE14.1, HSpice, Virtual Photonics, NI AWR Design Environment, ... - 2017 Feb 27
... ARM Processor SKILLS Programming Languages : C, C++,Perl Hardware Languages : Verilog,VHDL,MATLAB EDA Tools : Cadence Virtuoso, Encounter, Design Vision, Prime Time, Xilinx ISE14.1, HSpice, Virtual Photonics, NI AWR Design Environment, ... - 2017 Feb 27
Engineer Test Cases
San Jose, CA
... & Administration and Cisco/Nortel Switch and router configurations, Designing and development of a 8-bit microprocessor-using cadence PROFESSIONAL EXPERIENCE Cisco Systems, Milpitas, CA – Aug 2015 to Present Solution Test QA Engineer Feature test, ... - 2017 Feb 27
... & Administration and Cisco/Nortel Switch and router configurations, Designing and development of a 8-bit microprocessor-using cadence PROFESSIONAL EXPERIENCE Cisco Systems, Milpitas, CA – Aug 2015 to Present Solution Test QA Engineer Feature test, ... - 2017 Feb 27
Engineer Software
Santa Clara, CA
... overlapping shapes to optimize the RC parasitic network, using Computa- tional Geometry algorithms 2010 - 2013 Senior Member of Consulting Sta, CADENCE Design System Key contribution: Multi-Threading the Parasitic Extraction ow of the QRC tool. ... - 2017 Feb 14
... overlapping shapes to optimize the RC parasitic network, using Computa- tional Geometry algorithms 2010 - 2013 Senior Member of Consulting Sta, CADENCE Design System Key contribution: Multi-Threading the Parasitic Extraction ow of the QRC tool. ... - 2017 Feb 14
Engineer Network
Palo Alto, CA, 94302
... Switches CISCO 2900, 3500,4500,5000,6500, Nexus 7k,5k,2k Simulation Tools Qualnet Developer, OPNET IT GURU, OPNET Modeler, Cadence Firewalls Juniper net screen (500/5200), Juniper SRX (650/3600), Pix (525/535), ASA (5520/5550/5580), Checkpoint, Palo ... - 2017 Feb 14
... Switches CISCO 2900, 3500,4500,5000,6500, Nexus 7k,5k,2k Simulation Tools Qualnet Developer, OPNET IT GURU, OPNET Modeler, Cadence Firewalls Juniper net screen (500/5200), Juniper SRX (650/3600), Pix (525/535), ASA (5520/5550/5580), Checkpoint, Palo ... - 2017 Feb 14
ASIC Design Engineer
Sunnyvale, CA
... Institute of Technology August 2008 – July 2012 Bachelor’s Degree in Electronics Engineering, 3.8 GPA Mumbai, India SKILLS: EDA Tools : Cadence-Virtuoso, Xilinx Vivado, OrCAD PSPICE, MATLAB, Visual Studio, Altera Quartus 13.0, ModelSIM Programming ... - 2017 Feb 03
... Institute of Technology August 2008 – July 2012 Bachelor’s Degree in Electronics Engineering, 3.8 GPA Mumbai, India SKILLS: EDA Tools : Cadence-Virtuoso, Xilinx Vivado, OrCAD PSPICE, MATLAB, Visual Studio, Altera Quartus 13.0, ModelSIM Programming ... - 2017 Feb 03