Design Electrical Engineering

Manoj Mohan acy2j6@r.postjobfree.com

Seeking a full-time job opportunity in an environment 408-***-**** which provides more avenues in the fields of VLSI, 515 E Washington Ave Apt 515 ASIC and Computer Architecture Sunnyvale, CA 94086 Education

Master of Science in Electrical Engineering 08/2014 – 08/2016 University of Texas at Dallas, Richardson, TX GPA: 3.55/4.00 Bachelor of Science in Electronics and Communication 09/2007 – 06/2011 PES Institute of Technology, Bengaluru, India GPA: 8.12/10.00 Skill Set

Language : C, C++, Verilog, VHDL, System Verilog, Perl, TCL, HSpice Software &

IDEs

:

Cadence – Virtuoso, Encounter, Assura, Quantus RC; Synopsys – Design Vision, SiliconSmart, StarRC, PrimeTime, AtopTech - Aprisa, ModelSim, Xilinx, Quartus, Tetramax, Matlab, LabView, Keil, Visual Studio Certifications : Certified LabVIEW Associate Developer (CLAD) MSEE Coursework

VLSI Design, Advanced VLSI, Computer Architecture, Design and Analysis of Reconfigurable Systems (FPGA), Testing and Testable Design (DFT), Advanced Digital System, Hardware Security Work Experience

SSR Labs, San Mateo, CA – ASIC Design Intern 11/2016 – Present

Design of mantissa multiplication of Quadruple Precision Floating Point for Fused Multiply Add Unit (FMA) Broadcom Corporation, San Jose, CA – IC Design Intern 08/2015 – 12/2015

Physical design of chips of multimillion gates at block level using 16nm FinFET technology, starting from floor-planning to PnR and taking it through CTS and Routing.

Worked on timing closure, review timing reports and physically close timing at the block level, ECOs for fixing timing issues and Physical Verification for clearing up DRCs, LVS Bharat Electronics Limited, Bengaluru, India – Deputy Engineer 09/2011 – 06/2014

Developed Application Software for Communication Systems used by Indian Naval Ships and Submarines.

Developed the simulator for communication protocol of Radio Receiver EK896 and MSK Demodulator in LabVIEW.

Created an automated test suite to perform Acceptance Test for PC104 Board for the integrated product in LabVIEW. Academic Projects

RTL design of Customized Pipelined Microprocessor on FPGA Implemented a pipelined microprocessor on Nexys 4 DDR Board and interfaced with keyboard to take inputs from the user and display the output on VGA Monitor

8-T SRAM Design

Manual Placement and Routing of SRAM architecture of 256 words with 8-bit word size using IBM 130nm Technology with pre-decoded style of row decoder using Cadence Virtuoso and verified the functionality using Hspice.

ASIC Design flow of Booth Multiplier using Standard Cell Libraries Designed using Verilog and obtained Netlist using Synopsys – Design Vision, Equivalence check of RTL and Netlist using ModelSim, Layouts of basic gates and flops using Virtuoso, characterized library using Synopsys - SiliconSmart and performed APR using Encounter and verified functionality by Hspice simulation and ModelSim. Used PrimeTime for STA.

Customized Design of 14b x 14b Multiplier

Design and manual routing of Multiplier using Booth-2 algorithm which includes Compressors and Kogge Stone Adder to minimize power and delay. Functional verification using Hspice and WaveView. Used PrimeTime for STA.

Cache Design Optimisation

Designed a Cache with optimum configuration in relation to the cost function and the CPI for the Alpha 21264 EV6 configuration using the SimpleScalar tool for the given benchmark.

Implementation of an Arbiter PUF Circuit on a FPGA for Hardware Based Encryption Designed and implemented a Physically Unclonable Function (PUF) for providing hardware based encryption and authentication on Xilinx Spartan-3 FPGA in Verilog. The inter-hamming distance achieved was 44%.

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