| Resume alert | Resumes 171 - 180 of 450 |
Engineer Design
San Jose, CA
... Proficient in verilog and Hspice - Experience in Modelsim and ncverilog 2005 to Current Senior Staff ASIC Design Engineer Marvell Technology Company – Boise, Idaho Led and managed synthesis design team to work on a large and complex design in 28nm. ... - 2017 Feb 28
... Proficient in verilog and Hspice - Experience in Modelsim and ncverilog 2005 to Current Senior Staff ASIC Design Engineer Marvell Technology Company – Boise, Idaho Led and managed synthesis design team to work on a large and complex design in 28nm. ... - 2017 Feb 28
Design Electrical Engineering
San Jose, CA
... Bachelors of Engineering in Electronics and Communication CGPA 9.02 /10 DR.AMBEDKAR INSTITUTE OF TECHNOLOGY, BANGALORE, INDIA June 2014 Related Coursework: Digital System Design using Verilog, Fundamentals & Design of Logic Circuits, Embedded System ... - 2017 Feb 27
... Bachelors of Engineering in Electronics and Communication CGPA 9.02 /10 DR.AMBEDKAR INSTITUTE OF TECHNOLOGY, BANGALORE, INDIA June 2014 Related Coursework: Digital System Design using Verilog, Fundamentals & Design of Logic Circuits, Embedded System ... - 2017 Feb 27
Engineer Test Cases
San Jose, CA
... Languages & Operating Systems Pyats, python, Autoeasy, TCL, SHELL, EXPECT, Jenkins, PERL, Verilog HDL, C, Linux, HTML, JavaScript, Solaris & Windows Test Instruments and Analyzers Ethernet – Spirent, Ixia, IxNetworks, IxLoad, tcpdump, wireshark ... - 2017 Feb 27
... Languages & Operating Systems Pyats, python, Autoeasy, TCL, SHELL, EXPECT, Jenkins, PERL, Verilog HDL, C, Linux, HTML, JavaScript, Solaris & Windows Test Instruments and Analyzers Ethernet – Spirent, Ixia, IxNetworks, IxLoad, tcpdump, wireshark ... - 2017 Feb 27
ASIC Design Engineer
Sunnyvale, CA
... - Skilled in static timing analysis, FPGA Design Flow, Verilog coding, ASIC Design, CDC concepts, FSM Design, Fault Testing. - Knowledgeable in Backend VLSI, Design Verification, Routing Algorithms, DRC, LVS, Low Power Design, Physical Verification ... - 2017 Feb 03
... - Skilled in static timing analysis, FPGA Design Flow, Verilog coding, ASIC Design, CDC concepts, FSM Design, Fault Testing. - Knowledgeable in Backend VLSI, Design Verification, Routing Algorithms, DRC, LVS, Low Power Design, Physical Verification ... - 2017 Feb 03
Engineer Design
San Jose, CA
... - Developed various checkers in System Verilog to assert the proper scheduling and timing constraints of various complex features. - Used System Verilog language to write the diags that would validate the proper working of the blocks in VMM ... - 2017 Feb 01
... - Developed various checkers in System Verilog to assert the proper scheduling and timing constraints of various complex features. - Used System Verilog language to write the diags that would validate the proper working of the blocks in VMM ... - 2017 Feb 01
RTL,Verification,Bug fixing,Testplan,Testcase,Regression,SOC,Sumulatio
Sunnyvale, CA
... Expertise in Verilog and System Verilog Coding for development of and asic verification environment. Experience in verification of ARM based SoC. (System on Chip) at RTL level and gate level. Have Expertise knowledge of FPGAs and ASICs. Good working ... - 2017 Jan 30
... Expertise in Verilog and System Verilog Coding for development of and asic verification environment. Experience in verification of ARM based SoC. (System on Chip) at RTL level and gate level. Have Expertise knowledge of FPGAs and ASICs. Good working ... - 2017 Jan 30
HTML5, CSS, JavaScript, PHP, Python
San Jose, CA
... • Assembled the System Hardware on a daily basis to provide to the staff members of 5 departments • Troubleshoot PC hardware and software for employee PROJECTS • Title: ALU using Verilog HDL Summer 2015 Course: Computer Architecture Supervisor: Dr. ... - 2017 Jan 22
... • Assembled the System Hardware on a daily basis to provide to the staff members of 5 departments • Troubleshoot PC hardware and software for employee PROJECTS • Title: ALU using Verilog HDL Summer 2015 Course: Computer Architecture Supervisor: Dr. ... - 2017 Jan 22
Manager Project, Soccer and Badminton
Cupertino, CA
... (ASIC, Milpitas) 3/2001 – 6/2002 Member of Technical Staff • Implemented cell base custom ASIC design flow by manually coding gate level Verilog and physical cell placement using in-house tools. • Participated in entire physical design flow starting ... - 2017 Jan 15
... (ASIC, Milpitas) 3/2001 – 6/2002 Member of Technical Staff • Implemented cell base custom ASIC design flow by manually coding gate level Verilog and physical cell placement using in-house tools. • Participated in entire physical design flow starting ... - 2017 Jan 15
Engineering Engineer
Milpitas, CA, 95035
... Programming Languages: Verilog, System Verilog, VHDL, C, C++, Python, MATLAB, LabVIEW, Perl (beginner), SQL and SAS. Layout editor Tools: Magic. Operating Systems: Unix/Linux, Windows. EXPERIENCE TEST ENGINEER TESSOLVE SEMICONDUCTORS PVT LTD. Client ... - 2017 Jan 12
... Programming Languages: Verilog, System Verilog, VHDL, C, C++, Python, MATLAB, LabVIEW, Perl (beginner), SQL and SAS. Layout editor Tools: Magic. Operating Systems: Unix/Linux, Windows. EXPERIENCE TEST ENGINEER TESSOLVE SEMICONDUCTORS PVT LTD. Client ... - 2017 Jan 12
Electrical Engineering Systems
Redwood City, CA
... Implemented using Verilog Compiler Design Project: Designed a Compiler to C++ language to produce MIPS assembly code used Linux Operating Systems and Compiler generator tools lex and yacc. Directory-based Cache Coherence Protocol for Power-Aware ... - 2017 Jan 10
... Implemented using Verilog Compiler Design Project: Designed a Compiler to C++ language to produce MIPS assembly code used Linux Operating Systems and Compiler generator tools lex and yacc. Directory-based Cache Coherence Protocol for Power-Aware ... - 2017 Jan 10