Engineer Design

MALAVIKKA RAMESH

** ******** ** #**** *****: 858-***-****

San Jose, CA - 95134 E-mail: acylrs@r.postjobfree.com H1-B visa status LinkedIn - https://www.linkedin.com/in/malavikkaramesh OBJECTIVE

Actively seeking Full Time opportunities in the field of VLSI Verification/Design/Computer Architecture.

- 5+ months work experience as a Pre-Silicon Verification Engineer

- 1+ year work experience as Post Silicon Validation Engineer

- Working experience in UNIX/LINUX and PERL scripting languages WORK EXPERIENCE

Pre-silicon Verification Engineer, Oracle Microelectronics (September 2016 to present) Globals Verification Team

- Validated the functioning of STICK which is a timer that keeps track of real world time in the chip as a standalone cluster and full chip level function.

- Validated the Globals error Unit and its interfaces across the different blocks in the chip.

- Developed various checkers in System Verilog to assert the proper scheduling and timing constraints of various complex features.

- Used System Verilog language to write the diags that would validate the proper working of the blocks in VMM methodology.

- Developed the testplan, methodologies and models for validating functional compliance and feature integrity of the above mentioned clusters.

Post silicon Validation Engineer, Oracle Microelectronics (March 2015 to August 2016) Validation of Power Management Controller block

- Validated the over-temperature and over-current protection using Dynamic Voltage and Frequency Scaling technique

- Validated the operation of the chip at optimum Frequency under all load conditions

- Wrote scripts to verify the proper calibration of on-chip temperature sensors

- Developed a data collection infrastructure to poll power management controller data from the chip, process and upload it to a database. Queried this database and published the results in a PHP based webpage to identify anomalies

- Worked to successfully emulate/validate complex multi-core processors by focusing on functional, stress and performance validation

- Met project timelines and interacted with cross-functional teams for dependencies to resolve issues. EDUCATION

University of California, Santa Barbara Sep 2013 to Dec 2014 M.S in Computer Engineering GPA: 3.81/4

Relevant coursework: Advanced Computer Architecture – Processor Design, Basic VLSI Principles, Advanced VLSI Architecture and Design, Mobile Embedded systems, CAD of VLSI, VLSI Project Design, High Speed Digital IC Design, VLSI testing techniques. SSN College of Engineering (Affiliated to Anna University, Chennai, India) May 2013 B.E in Electrical and Electronics Engineering GPA: 8.93/10 Relevant coursework: Digital Logic Circuits, Microprocessors and Microcontrollers, Electronic Devices and Circuits, Linear Integrated circuits

SKILL SET

Tools: Synopsys DC, VCS, Verdi Cadence: Virtuoso, Encounter, Calibre; Mentor Graphics: Calibre DRC, DRV, LVS and PEX, ModelSim; MATLAB, MAX, SUE, HSPICE

Languages: C, C++, Perl, Python, Verilog HDL, SystemVerilog ACADEMIC PROJECTS

Design of Superscalar Instruction Dispatch unit using Tomasulo Algorithm (November 2013) Modeled a Super Scalar Instruction dispatch unit in Verilog. Resolved the RAW, WAR and WAW hazards by register naming technique. The design executes the ADD, MUL, FETCH and STORE instructions. Design of Multiprocessor Cache hierarchy (October 2013) Modeled a Multi-Level cache hierarchy system (Level 1 and Level 2) in Verilog. Implemented Snooping protocol to maintain coherence in all cache levels.

Design of Superscalar processor using Completion File (December 2013) Implemented this project similar to the dispatch unit with Tomasulo’s Algorithm above, but this design is made to handle Adder or Multiplier overflows and Page Fault during memory access using a Completion file. Logical verification and Fault coverage in RISC 1200 processor (March 2014) Synthesized various modules of the RISC 1200 processor using Synopsys Design Compiler tool and checked for Logical Equivalence and Fault Coverage.

Design of 16-bit second order Sigma Delta DAC (June 2014) Built a 2-channel all Digital DAC with SPI Interface that can be used for audio applications in 0.6um technology from RTL to GDS. Simulated and tested the final design with parasitic. Automatic Test Pattern Generation for ISCAS circuits (May 2014) Used SAT and OBDD to generate test patterns and for single fault models with multiple fanout logic. Analysis of Retention time and its dependence on Temperature and Height of Fin in a FinFET based Capacitorless 1T DRAM Cell

(May 2014)

Proposed a 1 transistor capacitorless DRAM cell design using FinFET. Transient analysis was performed and the variation of retention time with temperature and height of fin was studied. Design of 300Mhz clock tree for a die in 0.18um technology (February 2014) Designed a clock tree using H-tree and Minimum Spanning Tree suitable for driving 1.25M flip flops on the chip to keep the rise time and jitter+skew values within 300pS and 700pS respectively at the leaf nodes. Design of 16-bit Full adder using Low Voltage Swing Technology (November 2013) Designed a high performance 16-bit carry skip adder using SUE and HSPICE based on 90nm technology. Analyzed the critical path delay for different supply voltages, temperatures and technologies. PRIOR WORK EXPERIENCE

Research student at UC Santa Barbara (June 2014 to Dec 2014) Implemented a Network on Chip in Verilog

Teaching Assistant at UC Santa Barbara (June 2014 to Dec 2014) CS 8 – Python Programming

PHY6AL – Introduction to experimental physics

AWARDS AND HONORS

- Received the Chairman medal for academic excellence in the Electrical and Electronics Engineering department of Anna University, Tamil Nadu, India.

- Awarded a Full fee waiver and a gold medal for topping the department in the Junior year of Undergraduate education. PUBLICATIONS AND PRESENTATIONS

‘Power Saving in AC Systems using Solar cells’, published in the International Journal on Science and Innovative Engineering, May 2012.

‘Power Saving in Solar Powered Fan Drives’, presented in the National Conference on Recent Trends in Electric Power, Drives and Control, IEEE Madras section, March 2012.

Contact this candidate