| Resume alert | Resumes 161 - 170 of 513 |
Electrical Engineer
San Jose, CA
... RELEVANT COURSEWORK Embedded Systems Analog Circuits Computer Architecture Microprocessor Design Fundamentals of Modern VLSI devices Digital Systems Design Digital Signal Processing Electronic Device SKILLS Cadence, P-Spice (OrCad), knowledge of ... - 2017 Aug 30
... RELEVANT COURSEWORK Embedded Systems Analog Circuits Computer Architecture Microprocessor Design Fundamentals of Modern VLSI devices Digital Systems Design Digital Signal Processing Electronic Device SKILLS Cadence, P-Spice (OrCad), knowledge of ... - 2017 Aug 30
Design Electrical Engineering
Santa Clara, CA
... (Mailboxes, Queues, Virtual Interfaces, Assertions, Semaphores, Randomised Constraints, Covergroups), Python, UVM, QuestaSim, Cadence Virtuoso, Xilinx ISE, Altera Quartus II, Perl, MATLAB, Formal Verification using LEC and Model Checking, Machine ... - 2017 Aug 18
... (Mailboxes, Queues, Virtual Interfaces, Assertions, Semaphores, Randomised Constraints, Covergroups), Python, UVM, QuestaSim, Cadence Virtuoso, Xilinx ISE, Altera Quartus II, Perl, MATLAB, Formal Verification using LEC and Model Checking, Machine ... - 2017 Aug 18
Design Engineer
San Mateo, CA
... Mixed Signal Design and analog PCB Design using Cadence Design System – Allergo PCB and CAD Interface / tool. • Working with middle and upper management, managing resources (people / setup / lab time) spread across various teams and geographic ... - 2017 Aug 17
... Mixed Signal Design and analog PCB Design using Cadence Design System – Allergo PCB and CAD Interface / tool. • Working with middle and upper management, managing resources (people / setup / lab time) spread across various teams and geographic ... - 2017 Aug 17
Masters of Science
San Jose, CA
... Software: Cadence Virtuoso, Cadence Schematic Entry, Cadence Layout Suite, LTSpice, Silvaco, Calp, Keil, Xilinx, Solid edge, Solid works. Academic Projects Thesis project: Fabrication of multichannel electrodes on optical fiber substrate. Jan 2016- ... - 2017 Aug 11
... Software: Cadence Virtuoso, Cadence Schematic Entry, Cadence Layout Suite, LTSpice, Silvaco, Calp, Keil, Xilinx, Solid edge, Solid works. Academic Projects Thesis project: Fabrication of multichannel electrodes on optical fiber substrate. Jan 2016- ... - 2017 Aug 11
Design Electrical Engineering
Newark, CA, 94560
... EDA Tools: Cadence RTL compiler, Synopsys Design compiler, IC compiler, TetraMax, DFT, BSD. Programming Languages: C, C++. Others: HSPICE, IRSIM, Magic Layout Editor, Matlab, Modelsim, Xilinx, Linux. ACADEMIC PROJECTS Design of N-bit Array sorter, ... - 2017 Aug 10
... EDA Tools: Cadence RTL compiler, Synopsys Design compiler, IC compiler, TetraMax, DFT, BSD. Programming Languages: C, C++. Others: HSPICE, IRSIM, Magic Layout Editor, Matlab, Modelsim, Xilinx, Linux. ACADEMIC PROJECTS Design of N-bit Array sorter, ... - 2017 Aug 10
Engineer Marketing
Fremont, CA
... Dolphin Technology, San Jose, CA 07/2002~03/2003 IC Layout Design Engineer Use Cadence Virtuoso Layout Editor, Mentor Calibre to process DRC and LVS (Rule: UMC, TSMC, IBM) for different schematic projects. General Line, Saratoga, CA 11/2001~04/2002 ... - 2017 Aug 03
... Dolphin Technology, San Jose, CA 07/2002~03/2003 IC Layout Design Engineer Use Cadence Virtuoso Layout Editor, Mentor Calibre to process DRC and LVS (Rule: UMC, TSMC, IBM) for different schematic projects. General Line, Saratoga, CA 11/2001~04/2002 ... - 2017 Aug 03
Design Test
Santa Clara, CA
... techniques Programming Languages: VHDL, Verilog, C, C++, Python, Embedded C, Assembly, MPI, OpenMP, LabVIEW Tools: Cadence (Spectre, Vituoso, SOC Encounter, ICFB), Synopsys Design Compiler, ModelSim, Xilinx Vivado/ISE, TINA-TI, Aldec Active ... - 2017 Aug 02
... techniques Programming Languages: VHDL, Verilog, C, C++, Python, Embedded C, Assembly, MPI, OpenMP, LabVIEW Tools: Cadence (Spectre, Vituoso, SOC Encounter, ICFB), Synopsys Design Compiler, ModelSim, Xilinx Vivado/ISE, TINA-TI, Aldec Active ... - 2017 Aug 02
Data Scientist
San Jose, CA
... with external and internal partners -Coordinated internally & externally to define, document, and execute the setup, quality, cadence, and method of delivery of data files -Troubleshoot and problem-solving technical/data-related issues identified ... - 2017 Jul 26
... with external and internal partners -Coordinated internally & externally to define, document, and execute the setup, quality, cadence, and method of delivery of data files -Troubleshoot and problem-solving technical/data-related issues identified ... - 2017 Jul 26
Manager State University
San Jose, CA
... Linux Layout Tools: Cadence Virtuoso Layout Editor (VLE), Virtuoso XL Layout Editor Cadence Assura DRC/LVS/Soft-Check, Dracula DRC/Dracula, Chip Assembly Router Applications: MS Word/Excel Language: Fluent in Japanese San Jose State University: B.S. ... - 2017 Jul 24
... Linux Layout Tools: Cadence Virtuoso Layout Editor (VLE), Virtuoso XL Layout Editor Cadence Assura DRC/LVS/Soft-Check, Dracula DRC/Dracula, Chip Assembly Router Applications: MS Word/Excel Language: Fluent in Japanese San Jose State University: B.S. ... - 2017 Jul 24
Professional Experience Project
San Jose, CA
... SKILLS: * Layout Tools: Mentor, Cadence, Virtuoso XL, Linux Operating Systems. * DRC/LVS Tools: Caliber, Hercules, Assura. PERSONAL: Hard working, Organized, Patient and Quick Learner. . REFERENCE: Available upon request. - 2017 Jul 18
... SKILLS: * Layout Tools: Mentor, Cadence, Virtuoso XL, Linux Operating Systems. * DRC/LVS Tools: Caliber, Hercules, Assura. PERSONAL: Hard working, Organized, Patient and Quick Learner. . REFERENCE: Available upon request. - 2017 Jul 18