| Resume alert | Resumes 181 - 190 of 450 |
Engineer Test
Milpitas, CA, 95035
... TECHNICAL SKILLS: Coding Languages: Verilog HDL, VHDL, C Scripting Languages: Perl, TCL, Shell Scripting Operating System: Linux, Microsoft Windows XP, Solaris EDA Tools and Test formats: Synopsys Tools - DC and DFTCMAX, TETRAMAX, VCS, FORMALITY ... - 2017 Jan 05
... TECHNICAL SKILLS: Coding Languages: Verilog HDL, VHDL, C Scripting Languages: Perl, TCL, Shell Scripting Operating System: Linux, Microsoft Windows XP, Solaris EDA Tools and Test formats: Synopsys Tools - DC and DFTCMAX, TETRAMAX, VCS, FORMALITY ... - 2017 Jan 05
Design Electrical Engineering
San Jose, CA
Bo Pang 626-***-**** acxg4p@r.postjobfree.com *** ******* **** **., *** Jose, CA 95119 SUMMARY Over 4 years’ experience in semiconductor device and digital design area, new master graduate student in EE, proficient in HDL(Verilog) and HVL ... - 2016 Nov 12
Bo Pang 626-***-**** acxg4p@r.postjobfree.com *** ******* **** **., *** Jose, CA 95119 SUMMARY Over 4 years’ experience in semiconductor device and digital design area, new master graduate student in EE, proficient in HDL(Verilog) and HVL ... - 2016 Nov 12
Manager Data
Mountain View, CA
... Sr R&D Eng I Synopsys Inc Mountain View, CA 2006-2012 ● Developed Memory Pool Manager, System Verilog transpiler ● Developed emacs/elisp regression and analysis major and minor mode suites. ● Maintained Verilog, System Verilog, Qt, spice, and system ... - 2016 Oct 26
... Sr R&D Eng I Synopsys Inc Mountain View, CA 2006-2012 ● Developed Memory Pool Manager, System Verilog transpiler ● Developed emacs/elisp regression and analysis major and minor mode suites. ● Maintained Verilog, System Verilog, Qt, spice, and system ... - 2016 Oct 26
Test Engineer Manual
Los Gatos, CA
... 7.5, LoadRunner 7.51, Silk Test 5.3, Spectrum Analyzer Agilent 8591C Languages: C/C++, Python, Perl, Shell Script, Java, Verilog, HTML, XML Bug Tracking: JIRA,Clear Quest, Test Director, File Maker Pro, Bug Tracker, Bugzilla, Clarify Experience: 12 ... - 2016 Oct 21
... 7.5, LoadRunner 7.51, Silk Test 5.3, Spectrum Analyzer Agilent 8591C Languages: C/C++, Python, Perl, Shell Script, Java, Verilog, HTML, XML Bug Tracking: JIRA,Clear Quest, Test Director, File Maker Pro, Bug Tracker, Bugzilla, Clarify Experience: 12 ... - 2016 Oct 21
Electrical Engineering Design
Fremont, CA
... Knowledgeable in SOC level verification in system Verilog and C. Technical Expertise Programming languages : VHDL, VLSI. Communication Protocols : GNS3, MPI, RS232. Lay-out Tools : Advanced Model Sim, Matlab, Vivado, Xilinx ISE. Tools : Microsoft ... - 2016 Oct 17
... Knowledgeable in SOC level verification in system Verilog and C. Technical Expertise Programming languages : VHDL, VLSI. Communication Protocols : GNS3, MPI, RS232. Lay-out Tools : Advanced Model Sim, Matlab, Vivado, Xilinx ISE. Tools : Microsoft ... - 2016 Oct 17
Electrical Engineer Engineering
San Jose, CA
... TECHNICAL SKILLS C / C++ language, Verilog, SystemVerilog, VHDL, Python, shell script, Perl, TCL. FPGA, RTOS, OOP, Linux, embedded systems, TCL console, Timing closure, SPI, I2C, TCP/IP. WORK EXPERIENCE Software Engineer, Supermicro, 2015-2016.7 ... - 2016 Oct 08
... TECHNICAL SKILLS C / C++ language, Verilog, SystemVerilog, VHDL, Python, shell script, Perl, TCL. FPGA, RTOS, OOP, Linux, embedded systems, TCL console, Timing closure, SPI, I2C, TCP/IP. WORK EXPERIENCE Software Engineer, Supermicro, 2015-2016.7 ... - 2016 Oct 08
Verification Engineer
San Jose, CA
... Helped develop functional checkers and coverage for interface like 10G for Ethernet Professional Skills Languages: System Verilog, Verilog, UVM, basic concepts of C++. Tools: QuestaSim, IUS, VCS, Eplanner (Test Plan Creation), Emanager(Regression), ... - 2016 Oct 03
... Helped develop functional checkers and coverage for interface like 10G for Ethernet Professional Skills Languages: System Verilog, Verilog, UVM, basic concepts of C++. Tools: QuestaSim, IUS, VCS, Eplanner (Test Plan Creation), Emanager(Regression), ... - 2016 Oct 03
Project Coordinator/Analyst/Technical Writer
Sunnyvale, CA
... Agile Project Management, Scrum, Lean Agile Project Management, Waterfall Project Management Programming Skills – C, VHDL, Verilog Business Analysis – Requirement Gathering, SDLC, BRD, Test cases document Software – Microsoft Project, Office, Visio ... - 2016 Sep 26
... Agile Project Management, Scrum, Lean Agile Project Management, Waterfall Project Management Programming Skills – C, VHDL, Verilog Business Analysis – Requirement Gathering, SDLC, BRD, Test cases document Software – Microsoft Project, Office, Visio ... - 2016 Sep 26
Engineer Design
San Jose, CA
... Defense Research and Development Organization - Intern - Bangalore, India Jan 2013 Jun 2013 Designed a FPGA based dual redundant system and Verified UART and serial communication protocols using basic Verilog testbench SKILLS SKILLS: SystemVerilog ... - 2016 Sep 21
... Defense Research and Development Organization - Intern - Bangalore, India Jan 2013 Jun 2013 Designed a FPGA based dual redundant system and Verified UART and serial communication protocols using basic Verilog testbench SKILLS SKILLS: SystemVerilog ... - 2016 Sep 21
Electrical Engineering Manager
San Jose, CA, 95121
... •Software: KAREL, keil, ARM, Maple, Matlab, LTSPice, C++, Verilog, Quartus, Pascal, Excel, Word, Power Point, Photoshop, Premier, Dreamweaver, Final Cut. Additional Experience Creator and owner, earthtone enterprise January 11 – current •Received ... - 2016 Sep 17
... •Software: KAREL, keil, ARM, Maple, Matlab, LTSPice, C++, Verilog, Quartus, Pascal, Excel, Word, Power Point, Photoshop, Premier, Dreamweaver, Final Cut. Additional Experience Creator and owner, earthtone enterprise January 11 – current •Received ... - 2016 Sep 17