Design Engineer Ph D
Resume:
NICK ILIEV, Ph.D.
Round Lake Beach, Illinois 60073
ad9r7a@r.postjobfree.com
SUMMARY
Design Engineer of ASIC and FPGA systems, subsystems, and modules for a variety of applications. Considerable experience in hardware definition, design, and verification with applications in CPU, SoC ARM, and PCIe-DMA data transfer architectures, bus/memory controllers, embedded DSP (HLS) receivers, transmitters, and modems for 2G, 3G, and 4G cellular radio systems and embedded Processor systems. Proven abilities in designing DSP and Processor peripheral hardware modules in ASIC/FPGA, writing test benches, supporting module implementations, and developing behavioral models. Strengths in working with teams and mentoring. Analytical, and detail-oriented with focus on goals and results. 2 US Patents issued with 12 pending at Freescale (NXP) Semiconductors, Motorola SPS, Intel, IBM, and Univ. of Illinois. WORK EXPERIENCE
Lockheed Martin, Denver, Colorado 2024 - present
Senior ASIC FPGA Design Engineer
• Versal-ACAP FPGA processors for high speed, high bandwidth sensor/detector arrays and RFIC applications. Completed a custom SystemVerilog/Verilog architecture for ARM AXI4-Stream data link processing for Aurora 64b/66b multi-Gigabit Serdes optical transceiver links.
Canon Medical Research USA, Vernon Hills, Illinois 2019 – 2024 Senior ASIC FPGA Design Engineer
• Completed ASIC Arbiter modules Formal verification with System Verilog Assertions
(SVAs, classes, coverage, constraints, interfaces) in Cadence Jasper and in Synopsys VC- Formal.
• Completed Ph.D. level research in 128-way VLIW SIMD micro-architecture for DNN inference acceleration with HBM2 sub-system interface. An ISA instruction-extension can be used to control the accelerator. The accelerator can be added to a Tomasulo Out-of- Order-execution in-order completion pipeline.
• Completed Ph.D. level research in a novel conditional branch predictor micro-architecture, using a Perceptron and 128-bit History Buffer. Gem5 architectural simulations show better or equal branch prediction performance than a standard GSHARE branch predictor.
• Completed Ph.D. level research in ASIC std cell flows, Cadence Innovus clock net routing, std cell place&route flows (row-based, or custom-keep-out obstacles based); work examples on Github :
https://github.com/niliev4/Innovus_NanoRoute_RT01_routed_testcases_Blocking- CLK_path
• Completed research in ASIC standard cell flow (CMOS gsclk45 Cadence process) for Random-Number generator, example on https://github.com/niliev4/rng_self_calib
`NICK ILIEV
• Completed research in ASIC standard cell flow for a low-power 4-bit ALU in FDSOI process, full schematics to layout (DRC, LVS, RC-extract, post-layout sim) flow, example in:https://github.com/niliev4/ALU_4_bit_4_ops_mitll_fdsoi_process/blob/main/ALU_4bit_ 4_ops_schematics_layout_report.pdf
• Completed research in analog circuits for ASIC cell flow (CMOS gpdk180 Cadence process) spiking neuron-synapse, in ADE-XL Spectre/HSpice Monte-Carlo simulator; work examples on Github: https://github.com/niliev4/Spiking_Neural_Synapse_CMOS180
• Completed research in analog circuits for ASIC mixed-signal cell flow (CMOS gpdk45 Cadence process), cell for 2D/3D linear system solvers; Synopsys HSpice; work examples on Github: https://github.com/niliev4/Analog-CMOS-Systems-and-circuits-for-2D-3D- Localization/blob/main/Analog_CMOS_systems_for_2D_3D_Localization_N_Iliev_UIC% 20_Tech_Report.doc
• FPGA designs for medical CT, PET, and MRI scanners. High speed PCIe-based DMA channel architectures for data acquisition and data processing for medical scanner sub- systems.
• Defined and implemented the FPGA-side of several product features, including :
• C/C++ HLS signal processing modules and implemented as signed fixed-point arithmetic with Vitis - Vivado for Ultrascale+ FPGAs. Applications to RF and Magnetic field sensing and control (MRI).
• ARM GIC (Zynq MPSoC) interrupt controller interfaces for various interrupt sources
(sensors) with multiple sample rates (MRI, CT, others).
• Power Amplifier (PA) control+status interfaces over multiplexed data and address PA bus
(MRI).
• Start/stop scan control logic (pre-scan calibration) for scan preparation and configuration.
• PCIe Gen3 x 8 endpoints with support for XDMA transfers to/from on-FPGA SRAM and to/from off-FPGA DRAM, under transfer constraints such as bandwidth, latency, and jitter.
• Versal-ACAP Ethernet MRMAC node with packet generator for link loop-back testing.
• Versal-ACAP AI-Engine DSP filters mapped with Model-Composer for parallel processing in a 7-way VLIW SIMD architecture.
• Completed ASIC Arbiter modules Formal verification with System Verilog Assertions
(SVAs, classes, coverage, constraints, interfaces) in Cadence Jasper and in Synopsys VC- Formal.
Cambium Networks, Rolling Meadows, Illinois 2018-2019 Senior ASIC FPGA Design Engineer
• Design and integration of a novel streaming LDPC encoder interface block for a 4G/5G
(600,900) code with Zc=60. The interface is low-latency ( approx. 80 cycles ) between 16- bit wide SRAM and 600 bits at the encoder input bus. The same interface block is reconfigured to connect the encoder output (900 bits ) to 16-bit SRAM.
• Contributed interface designs for a first successful LDPC link in a Canopy fixed wireless network. Implemented in Intel / Altera Cyclone V, Cyclone III and Quartus. Harris, Exelis, ITT, Des Plaines, Illinois 2008-2018 Senior ASIC FPGA Design Engineer
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• Developed circuits for satellite transceivers ( Iridium ) and modems, enhanced RX and TX digital baseband signal processing modules in Actel and Xilinx FPGAs and CPLDs, contributing to more design wins at customers.
• Experience with Xilinx Vivado Tools and 7-Series FPGAs : Clock Wizzard, FIFO Generator, FIR Compiler, Memory Compiler, PCIe generator, Matlab FDA tool, Simulink-HDL_Coder to Xilinx flow, Simulink System-Generator to Xilinx flow, AC701 Dev board, Zynq Dev board
• Developed Artix-7 FPGA based interleaver, deinterleaver, DMA-and FIFO based interrupt controller processor peripherals
• Experience with Xilinx ISE Tools and Spartan-6 FPGAs SP605 dev board, Epiq Maveriq board
• Experience with Microsemi/Actel Libero Tools and FPGAs – Synopsys Synplify, ModelSim
• Developed Matlab/Simulink models for channelizer ( wideband receiver ) capable of separating up to 256 frequency channels and downmixing each individual channel from IF to baseband. Floating-point and fixed-point models based on polyphase filters and FFT processor.
• Developed eFuse controller in FPGA to interface to ASIC-based eFuse block for personalizing ASIC functionality
• Developed SPI-based Inter-Processor Communications Mailbox system, in FPGA, for enabling two processor Mailbox based communications
• Developed QPSK modulator in FPGA, with LUT stored I Q waveforms with re-programmable shapes for desired spectral features for different speading modes.
• Developed interface logic for TI OMAP baseband processor integration, digital power- management and battery fuel gauge control, secure-supervisor watchdog functions, keypad and speaker control, and LCD interfacing to Marvell PXA display controller. Developed IF-to- baseband down-mixer and decimator for an Iridium ASIC application. FREESCALE SEMICONDUCTORS, Lake Zurich, Illinois 2004- 2008 Senior IC Design Engineer/ Digital Radio Transceivers
• Designed DSP hardware modules for GSM/EGPRS (2G) receiver and transmitter functions using Verilog HDL, Synopsys, and Cadence tool sets to include digital anti-aliasing filters, down/up-mixers, and channel selectivity filters to develop BlackBerry and 2G/3G cells.
• Developed module specifications ( SPW, ADS, Matlab system models ) and implemented models from HDL to final product, resulting in increasing client base and sales.
• Wrote testbenches in Vera, embedded C, and Verilog for block verification, leading to decreased defect count and improved functionality.
• Two issued patents on selectivity filter micro-architecture to increase company’s IP portfolio in channel filters.
• Developed and integrated DSP selectivity filter module for 3G WCDMA receivers and for 4G LTE receivers. Supported module’s implementation in final silicon contributing to project completion on schedule.
• Designed digital 8PSK modulator and pulse-generation block for 2G EGPRS transmitter, and supervised silicon implementation, improving system performance. Filed 1 patent disclosure.
• Designed digital fractional-N divider module for DPLL-based frequency generator and filed one patent disclosure on generator’s micro-architecture and silicon implementation, resulting in improved product performance.
• Developed digital configuration block for HC12 embedded controller with interfaces to on-chip SRAM, ROM, and to peripheral blocks ( IPBI bus peripherals), and supervised block’s silicon implementation to achieve proper system function.
• Wrote embedded C test code for peripheral block verification, resulting in reduced defect count and timely product delivery.
`NICK ILIEV
• Designed programmable bit-length SPI module for HC12 embedded system and supervised silicon implementation to increase product inter-operability and decrease overall system cost.
• Led verification effort for 2G GSM/EDGE transmitter sub-system and wrote behavioral models for analog/RF mixers, filters, and DACs using AMS, Verilog, and System Verilog resulting in decreased defect count and improved performance .
• Wrote Matlab/Simulink models for TX and RX I/Q equalization ( amplitude, phase) algorithms for more efficient system. (Filed 2 patent disclosures)
• Developed behavioral models for space-time and space-frequency encoders for 2TX 2RX MIMO diversity OFDM system and wrote floating-point Matlab space-time encoder/decoder model contributing to efficient system simulation.
• Designed several digital I/O control and digRF interface modules using Verilog and Lattice CPLD and FPGAs and developed logic for training sequence insertion in GMSK/EDGE bursts which interfaced with Labview/PC DAQ cards to evaluation boards with ASIC under test.
• Developed several serial to parallel interfaces for 2G digRF and 16-bit DAQ hardware, leading to improved test times and increased test system capability.
• Patent Application : LMS hardware accelerator for 4G OFDM comb-type channel estimation in the time domain
• Patent Application : Channel estimation hardware accelerator for time domain real FIR channel models
• Patent Application : GF multiplicative inverse/exponentiation hardware unit
• Patent Application : Distributed Systolic vector dot-product matrix-vector product hardware unit
• Patent Application : Digital low pass filter (LPFIR) with programmable order and coefficients
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MOTOROLA INC, SPS WMSG Division, Libertyville, Illinois 1997-2004 ASIC Design Engineer
• Designed block encoders and decoders (CRC, Fire, Reed-Solomon ) for 2G modem ASIC, which increased product capability and standards conformance. (Filed 2 patent disclosures)
• Designed convolution encoder and decoder (Viterbi ) for 2G modem ASIC utilizing 32 and 64- state parallel trellis structure, and supervised design’s migration into next-generation project, which improved design flow.
• Developed module for maximum-likelihood sequence estimation/detection for decision feedback equalizer reference model and increased module design reuse library.
• Developed Matlab model for FIR-type transversal equalizer based on adaptive LMS algorithm, which decreased system simulation time and allowed for reuse in other applications.
• Designed verilog pulse shaping filter for 16-QAM modulator application to improve product performance (area, power) and allow for design reuse in other projects.
• Developed verification testbench for GPS module (Mcore CPU peripheral), supported silicon implementation and wrote tests in C code for module verification to decrease defect count, improve performance, and contribute to several design wins at customers.
• Led development and verification of two ARM7 peripheral modules (AMBA peripherals), contributing to increased product functionality and competitiveness. (Filed 1 patent disclosure)
• Wrote tests in ARM assembly and C code for module verification and eveloped peripheral interface logic for TMS320 DSP XIO, and Motorola 56000 Onyx DSP embedded controllers, resulting in design wins at several customers and increased sales.
• Patent Application : Novel Verilog-XL mixed-signal simulator model for approximate simulation of analog biquad (IIR) filter stages and other analog network transfer functions which have to interface to digital buses.
`NICK ILIEV
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INTEL, MPG Division – Portland, Oregon, Santa Clara, California 1994-1997 Staff Design Engineer
• CPU design and verification for PentiumPro, MMX, EL2 cache, and Merced bus-controller sub-systems. VLSI CAD tools used – Synopsys Design Compiler, Verilog, Intel-HDL, iSIM, Timber-Wolf Place & Route, Primetime STA.
• Patent Application : Encoding of Symbolic Inputs in Serial Decomposition of PLAs ; area/speed optimization for random logic ASIC blocks IBM, Data Networks Division – RTP North Carolina 1989 1993 Associate Hardware Engineer
• Design and verification of fiber-optic token ring networks, with CPU-Transceiver interface in Xilinx CPLD and PCB.
• Patent Application : FDDI (optical fiber token ring) Station Manager controller architecture and topology map builder
EDUCATION
Ph.D. completed in EECS at Univ. Illinois Chicago 2014 – 2020 Advisor : prof. Trivedi – DNN/CNN hardware accelerators (VGG16, AlexNet inference), neuromorphic circuits and architectures for machine learning and spatial localization. Neuromorphic systems and algorithms for DSP, communications, machine learning, image processing, speaker and pattern recognition, with VLSI ASIC applications; IEEE publications on neural network for spatial localization, GPS and image-based localization and tag estimation, speaker recognition with kMeans online clustering, with applications to speech recognition, Bayesian networks, HMMs and sigma-point Kalman filtering, detection, and estimation Google Scholar publications link :
https://scholar.google.com/citations?user=4UCkbMYAAAAJ&hl=en GitHub link :
https://github.com/niliev4
https://github.com/niliev4/Spiking_Neural_Synapse_CMOS180 https://github.com/niliev4/rng_self_calib
Selected works :
Low Latency CMOS Hardware Acceleration for Fully Connected Layers in Deep Neural Networks N Iliev, AR Trivedi - arXiv preprint arXiv:2011.12839, 2020 Low-Power Sensor Localization in Three-Dimensional Using a Recurrent Neural Network N Iliev, AR Trivedi - IEEE Sensors Letters, 2019
Low Power Spatial Localization of Mobile Sensors with Recurrent Neural Network N Iliev, AR Trivedi
Computer Design (ICCD), 2017 IEEE International Conference on, 297-30
`NICK ILIEV
Accurate Image Based Localization by Applying SFM and Coordinate System Registration M Salarian, N Iliev, R Ansari
IEEE International Symposium on Multimedia (ISM) 2016, pp.189-192 Review and comparison of spatial localization methods for low-power wireless sensor networks N Iliev, I Paprotny
IEEE Sensors Journal 15 (10), 5971-5987
Communications-related graduate-level courses : Matlab model of MISO 2x1 uplink two-way relay model with symbol timing synchronization, and channel estimation. Wrote and verified Python and C++ code for Software-Defined-Receiver ( SDR ) MIMO platform, using GNU-Radio and USRP tools. Detailed technical report available on request. Patent Application : SOM Neural Network for IP packet switching and routing applications ;
“Flexible and High-Speed Packet Classification in Software Defined Networking using Self- Organizing Maps prof. Trivedi, prof. Vamanan, Iliev, Patent Application ; Nonlinear least-squares estimator ( Levenburg-Marquard ) architecture for 2D 3D angle-of-arrival based spatial localization, prof. Paprotny, Iliev 2015 Patent Application : Prostetic robotic glove with micro-sensors (MEMS) and processor (ARM) interface, prof. Zefran, Noohi, Iliev 2014
Patent Application : 2x2 MIMO Receiver and channel model and estimator, start-of-burst detector, and frame preamble based synchronization architecture, prof. Devroye, Iliev 2013 Coursework toward Ph.D. in Electrical Engineering, Lehigh Univ, Bethlehem, PA 1988-1991 Research topic: non-linear circuit simulation and Kalman filtering for signal detection and tracking. Verilog and VHDL implementation of discrete time/amplitude algorithms. M.S. Electrical Engineering, University of California, Irvine, CA 1987 Graduated with thesis on linear stochastic system models and signal detection methods. Verilog and VHDL implementations of DSP algorithms. B.S. in Electrical Engineering, Northwestern University, Evanston, IL 1986 Graduated with Honors, member Eta Kappa Nu.; Senior project ECG amplifier and data processing system
INTELLECTUAL PROPERTY, PAPERS, AWARDS
Patents: 2 US patents issued with US Patent Office, 12 patent applications in evaluation Circuit and method for generating fixed point vector dot product and matrix vector values https://patents.justia.com/inventor/nickolai-j-iliev Patent number: 8165214
Programmable phase mapping and phase rotation modulator and method https://patents.justia.com/inventor/nickolai-j-lliev Patent number: 7412008
Presentation: Asynchronous Logic DSP design, 2007 Freescale Design Conference
`NICK ILIEV
Paper Publications and Technical Reports :
https://scholar.google.com/citations?user=4UCkbMYAAAAJ&hl=en Algorithm-Hardware Co-Design for Low-Power Smart Home AI Devices Iliev, Nikolai.University of Illinois at Chicago. ProQuest Dissertations Publishing, 2020. 28334030. Low Power Spatial Localization of Mobile Sensors with Recurrent Neural Network N Iliev, AR Trivedi
Computer Design (ICCD), 2017 IEEE International Conference on, 297-30 Accurate Image Based Localization by Applying SFM and Coordinate System Registration M Salarian, N Iliev, R Ansari
IEEE International Symposium on Multimedia (ISM) 2016, pp.189-192 Review and comparison of spatial localization methods for low-power wireless sensor networks N Iliev, I Paprotny
IEEE Sensors Journal 15 (10), 5971-5987, 2015
2012 Thread Fair Memory Request Reordering Z Kun Fang, Nick Iliev, Ehsan Noohi, Suyu Zhang 3rd JILP Workshop on Computer Architecture, Energy Track 2010 Dynamic partially reconfigurable FPGA algorithm for a fault-tolerant systolic DSP array, technical report.
2005 IEEE Midwest Conference on Circuits and Systems (GF field divider circuits for BCH, Reed- Solomon codes )
2004 IEEE ISVLSI Conference on bit-parallel GF multipliers 1995 Portland State University Symposium on Logic Design Awards:
2014 Exelis eFuse controller project
2005 Freescale DSP Onyx SoC tapeout
2002 Motorola System's Simulation Symposium
1998 Motorola Texas Instrument Project, first dual-core SOC tapeout ( ARM7 and TMS320 SoC ) 1994 Intel MPG PentiumPro tapeout
1992 IBM RTP token ring project
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