Design Engineer Electrical

Tomer Saraf

**** * ******* ***. #**, Phoenix AZ *5020

480-***-****, aczktm@r.postjobfree.com

Electrical Engineer

Co-founded SolaRobot – developing an autonomous solar panel cleaning robot. Almost done and looking for my next challenge.

An analog/mixed-signal design engineer and team leader. Nine years of IC (Integrated Circuits) design and architecture experience, bringing detailed approach to design and problem solving while maintaining high level strategic overlook at the product level. Taped out various successful projects in advanced processes. Citizenship status: Green-Card holder.

Highlights

Design team leader

Delivering a product from concept to

production, achieving quality results under tight

schedules

Multi-disciplinary hands-on engineering,

prototyping and collaborating with other teams

Market research, literature search, system

architecture, defining specifications, design

reviews, defining validation procedures, lab

debug and failure analysis

Top-down system design approach, utilizing

Analog/Mixed-Signal (AMS) modeling

System analysis of data converters for high- end audio, utilizing Matlab/Simulink

Analog blocks circuit architecture (low noise, low power), design and optimization in advanced

processes

Extensive lab debugging experience, prototyping

and bring-up

Experience

Co-founder, Solarobot (http://solarobot-cleaner.com/?lang=en)

(June 2016 - ) Phoenix, AZ / Israel

With my brother, we are building an autonomous solar-panel cleaning robot. Involved with the business side and in charge of the embedded electronics: architecture and design of sensor interfaces (optical, accelerometer), motor control, power management (DC/DC), batteries (Li-Ion), control units (MCU, I2C, SPI, USB, UART) and communications (WiFi, GSM). Currently finalizing the last version of the electronics and starting selling the systems. Analog IC design team manager, Qualcomm (formerly CSR)

(January 2015 to May 2016) Tempe, AZ

Managing an experienced design team of 4 engineers responsible for developing the audio Intellectual Properties

(IPs) of the company. Developing and maintaining project schedules, risk analysis, resource allocation, long-term development plans, etc..

Top-down design flow from concept to product. Defining specification, system analysis of data converters

(ADCs / DACs), analog circuit topologies for low-power design in advanced processes, chip level integration, lab characterization and documentation.

Leading the development of a DAC/Class-D (Digital) amplifier for driving headphone loads. Achieving signal to noise ratio (SNR) of 100dB and total harmonic distortion (THD) of -90dB at much reduced power consumption

(5mW) compared to competition and with no external components (utilizing filter-free Pulse Width Modulation). Senior Analog IC design engineer, CSR

(October 2013 to December 2014) Tempe, AZ

Leading the analog system development of a high-end Class-D audio amplifier chip in a new process (high voltage 180nm). Achieving successful first tape-out with performance (SNR 115dB, THD -100dB) exceeding the spec requirements, making this chip a new state-of-the-art benchmark for its market segment.

My part in the design included system architecture, Sigma-Delta ADC modeling, top level simulations, transistor modeling study of the new process to utilize gm/ID design methodology and circuit design of the critical ADC’s first stage (low-noise amplifier for the first integrator). Tomer Saraf

8150 N Central Ave. #19, Phoenix AZ 85020

480-***-****, aczktm@r.postjobfree.com

Technical leading 2 design engineers, collaborating with power management, digital and software teams and guiding board designers. Hands on prototyping in the lab, optimizing overall system performance at customer level board, supporting validation and testing groups, etc.. Analog IC design engineer, CSR (formerly Zoran)

(November 2007 to September 2013) Haifa, Israel

Design lead of a 1st-order closed-loop low-power Class-D audio amplifier, low phase noise / low-power closed- loop Crystal oscillator, standby power management block.

Circuit design of operational amplifiers, reference blocks, linear regulators, ring-oscillators, clock trees, etc..

Most projects were high-volume and my role also included supporting SOC integration of analog blocks for multiple projects / tape-outs in various processes (40, 80, 90, 180nm) followed by extensive lab characterization, debug and failure analysis.

Board design internship, Elbit Systems

(June 2004 to July 2007) Haifa, Israel

Design of test equipment for avionics, lab testing and debug, circuit design improvement (analog and digital circuits), guiding PCB (printed circuit board) layout editor, working with FPGAs (Field Programmable Gate Array) and Power management, environment testing.

Education

Master of Science in Electrical Engineering, Technion

(2015) Haifa, Israel

Thesis subject - Study of analog readout circuits for uncooled infrared TMOS (Thermal Metal Oxide Semiconductor) sensors. Supervised by prof. Yael Nemirovsky. It included a study of the Technion’s TMOS sensor and the design of low-power / low-noise readout in CMOS-SOI (Silicon On Insulator) technology followed by a successful tape-out. Publication: CMOS-SOI-MEMS Uncooled Infrared Security Sensor With Integrated Readout, IEEE Electron Devices Society.

Bachelor of Science in Electrical Engineering, Technion

(2007) Haifa, Israel

Specialization groups: signal processing, microelectronics, biological systems and signals. Graduation project - VLSI Implementation of Realistic Neural Networks: implementing an Analog ASIC, extensive Matlab simulations of big networks (with the extracted analog circuit's behavior). Participated in short analog courses and seminars over the years, mainly in ACRC (acrc.ee.technion.ac.il) and also at EPFL (Switzerland).

Languages

Fluent in Hebrew and English

Skills

Cadence Virtuoso and Spectre, Matlab, Simulink, Calibre RC extraction, AMS modeling, MS-Project, PCB CAD

(Altium, Diptrace), Oscilloscopes, Logic-Analyzers, Audio-Precision and some RF lab equipment.

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