Design Engineer Management

Objective:

To obtain a position as a Physical Design Engineer in an esteemed organization that gives ample scope to fulfil professional and personal goals and to work for development of organization to the highest possible limit.

Professional Training:

Trained in VLSI Physical Design on Cadence Tools from Shastra Micro System, Hyderabad (January to August-2014).

Course outline:

VLSI Fundamentals, CMOS Basics, Digital Design, Logic Synthesis, Custom Layout, Floor Planning, Power Planning, Placement and Routing, clock tree synthesis, static timing analysis, OCV variation, cross talk analysis, MMMC flow and Physical Verification.

Tools:

Experienced in physical design of 180nm, 130nm and 65nm using Cadence tools

Cadence SOC Encounter – Floor Planning, Place & Route, and clock tree synthesis

RTL Compiler- Logic Synthesis

Virtuoso – Custom Layout

Encounter timing system – Static timing analysis and Cross talk analysis

Assura – Physical verification

RC extraction – QRC

Academic Qualifications:

Study

School/college

Board/university

Academic year

% of marks obtained

M.Tech (VLSI)

Institute of aeronautical engineering

JNTU-Hyderabad

2014

78.3%

B.E.(Electronics & Communication)

Chhatrapati shivaji institute of technology

CSVTU-Bhilai

2011

71.2%

12th

Saint josephs hr sec school

CGBSE

2007

77.2%

S.S.C

Saint josephs hr sec school

CGBSE

2005

90.2%

Projects:

Title: “DTMF DESIGN IMPLEMENTATION”

Tools: First Encounter (CADENCE)

Description: Implemented DTMF design in 180nm technology node using CADENCE FIRST ENCONTER .Understanding I/O pads arrangement, design constraints, Floor planning, Power planning, placement, CTS, Routing and bringing to timing closure and fixing DRC violations.

Design Metrics:

Technology : 180nm with 6 metal layers

Macro count : 4

Frequency : 150MHZ

No. clocks : 3

No. Instances / Nets : 6000/6274

Supply Voltage : 1.2v

Challenges:

Fixing floor plan to get minimum congestion (0.11%)

Resolving the TIMING issues in all stages of design

Extra-Curricular Activities:

Published a paper on “Reduction of dynamic power in L2 cache architecture using way tag information under write-through policy” in International Journal of Ethics in Engineering & Management Education (IJEEE).

Participated in paper presentation and quiz competitions conducted at College & University level. .

Was an organizing member of the LAkshya event in our college.

Technical Skills:

Operating Systems : Windows, Linux

Frontend Synthesis Tools : Cadence RTL Compiler.

Backend Synthesis Tools : Cadence SOC Encounter, ETS,

and QRC extraction.

Scripting Languages : Tcl.

Personal Profile:

Name : Richa Tiwari

Father’s Name : Ramesh Kumar Tiwari

Date of Birth : 6th sep 1990

Gender : female

Languages known : English, Hindi.

Strengths : Good Management Skills, Hard Working, Adaptability.

Declaration:

I hereby declare that all the details above are true to the best of my knowledge.

Date:

Place: (Richa Tiwari)

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