ASIC,Verilog, System verilog, UVM

SATISH JHAWAR

Email ID: acebh7@r.postjobfree.com Ph.No: 856-***-****

OBJECTIVE

Seeking an Fulltime in the field of computer architecture / VLSI design and verification where I can put my technical skills using my academic knowledge.

EDUCATION

Portland State University, Portland, OR (Expected Graduation June 2014)

M.S in Electrical and Computer Engineering (GPA: 3.6/4)

R.V.R&J C college of Engineering (May 2012)

B.T ech in Electrical and communication Engineering (GPA: 3.82/4)

ACADEMIC SUMMARY

• 6 month experience VLSI Design, RTL coding and Verification

• Advance Course work in CPU architecture, micro architecture,Digital circuit design and verification, Power analysis

• Good academic knowledge on ASIC Modeling and Synthesis, Logic/Verification Design, ASIC Physical Design

• Experience in C,C++,PERL,TCL,Verilog,System Verilog

• Exposure to Pre-Silicon Verification. Experience in test bench development and simulation for functional and coverage based verification.

• Academic experience with VLSI design relevant CAD tools such as Cadence ASIC tools

TECHNICAL SKILLS

• EDA and Simulation Tools: CADENCE, ModelSim.

• Hardware Languages: Verilog and VHDL.

• Programming Languages: C, C++.

• Scripting Languages: Perl,Bash,TCL

Power and Performance Engineer Intel -Intern (6 months)

• Performed and delivered Power and Performance (PnP) optimization by running CPU, GPU benchmarks across the different platforms for Tablets based on Intel Atom Processor.

• Analyzing thermal related workloads and collected different thermal parameter and contributed in developing new Thermal algorithm

• Acquiring and demonstrating knowledge of CPU C States and P States

• Debugging in the architectural level for the finding better solution/technique by checking the CPU register level data using tool tools like Perf monitor.

• Projecting and Building the Performance vs. Power curve . Analyzing and post processing system power and Graphics core rail power,CPU core rail power to give more detail of the given workload.

COURSE WORK

Microprocessor system Design Computer Architecture

ASIC: Modeling and Synthesis Digital Integrated Circuits

Pre-Silicon Validation Low Power IC Design

GRADUATE LEVEL PROJECTS

• Design and Layout of Digital CMOS circuits using cadence Tools.

Designed schematics and layouts for digital circuits. Performance analysis with delay area and power calculations. Circuit designs include CMOS inverter, AOI cells, NAND, NOR, LATCH, FLIPFLOP and OAI cells and also performed DRC and LVS to the Layout.

• Digital Design Automation using Perl

Wrote Perl scripts for Log file handling

Processing net list data from Verilog database

Developed Perl scripts to find the number of instantiation of particular standard library cell after synthesis

• Design for Testability

Determined the stuck at fault patter for a Adder circuit.

Generated the Input patterns that would detect faults at different nodes

Test Pattern Generation of Combinational Circuits Using Ordinary Algebra for Adder circuit

• Simulation and performance analysis of a 4-bit Arithmetic logic unit using Cadence Soc Encounter for place and route.

Wrote the Verilog code and used Cadence tools are for synthesis and auto place and route

Performed Timing analysis on the design and meet setup and hold time requirements

Performed the Pre layout and post layout analysis and performed clock Tree synthesis for the design.

• Low power Digital circuit design

Computed the Dynamic power and static power of combinational circuits using Probability Theorem’s.

Designed a Comparator with pre computation unit that saves power up to 50% than original design.

Designed circuit to reduce the power and understood bus encoding schemes which would reduce switching power

• Pre-silicon Verification of Split L1 cache.

Implemented a grey box testing by using a trace file generator to feed the inputs of the DUV and monitor its outputs and also monitored the internal components in order to make sure that it is functioning properly. Used pre-deterministic tests and random testing as a verification strategy.

• ASIC Modeling and Synthesis.

Designed FIFO and state machine, Understood the asynchronous design, implementation of the state machines, timing delay analysis and cost effective of ASIC design. RTL implementation of a specification, RTL simulation, Synthesis, gate level simulation, Familiar with ASIC design Flow. Synthesis and static timing analysis.

• Design and Simulation of Alpha based branch predictor and Branch target predictor.

Designing a tournament branching predictor and branch target predictor based upon the design employed by the alpha 21264 Microprocessor and simulate to print the statistics including misprediction rate.

• Design and simulation of L1 cache in multiprocessor system using MESI protocol.

Designed a L1 cache simulator (16k sets of 64byte lines and four way Set associative using LRU replacement policy) for a new 32- bit processor which can be used with up to three other processors in a shared memory configuration in a multiprocessor system using MESI Protocol.

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