Engineer Manager

VARUJAN (John) SAHAKIAN

Encino, CA. *****

Home Phone 818-***-****, Cell 818-***-****

Email acam0u@r.postjobfree.com

US Citizen

Summary:

Senior Principal/ EE lead Engineer with extensive experience in Hardware

System Architecture, Circuit Design, Project management, manufacturing,

PCB layout, and Testing. Seeking a project management and development lead

position that utilizes my strong background in SoC, CPU, FPGA and high

speed SerDes.

EXPERIENCE:

Western Digital, Irvine, CA. April/2011 -

Oct/2013

Senior Principal Engineer/EE Project Lead

EE project lead for multiple DAS, SMB, NAS Pedestal and Rack mount storage

system that includes controller design, backplane design, redundant power

supply, add-in PCIe WIFI module which utilizing various SoC (AMP86491,

Mindspeed M86261G SoC) and Intel Atom processor that supports multiple

SATA drives, DDR3 memory, USB3.0 ports, 1Gbps Ethernet ports, UART, PCI

Express etc.

Duty includes Project Management and Hardware development schedule,

management software bring-up code, Circuit design, PCB layout

support/routing constraint, Low cost/High volume production support in

Asia, characterization and validation.

Tools: DxDesigneer Schematic Entry, PAD layout, MS project

Curtiss Wright Embedded Computing, Chatsworth, CA Jan/2007 -

March/2011 .

Senior Principal Hardware Engineer

. Lead the Engineering Designed and developed activities for four Open-

VPX Vita46, 6U/3U form factor, REDI image processing DSP boards in the

past five years that supports dual FMC Vita 57 interfaces, XMC

interfaces, 10 Gbit/sec Ethernet, multiple high Speed SerDes

interconnect to the back-plane supporting PCI Express, sRIO, Rocket

IO, XAUI interfaces. Based on the MPC8640D processor and multiple

Xilinx Virtex6/Virtex5 FPGA's.

. Lead the PCB routing team that produce the PWB from start to finish

. All designs Supports the MPC8640 CPU, DDR3/DDR2 memory, QDR2+ SRAM,

Tundra TSI578 sRIO switch.

. Lead the Design and developed activities for Vita 42.x XMC/PMC

mezzanine memory buffer controller that provides high speed inter

connect such as PCIe X8/Dual X4 sRIO interfaces based on the Xilinx

Virtex 5 FPGA .

. PCB routing constraints are included in the schematic level using the

Cadence Allegro HDL expert software that specifies routing topology,

matching groups, Differential pairs and the electrical constraint set

rules including the DDR2/DDR3, high speed SerDes etc.

. Generate/Create all Allegro component symbols used in the design.

. Perform all PCB Design and routing using for all re-spin boards using

Allegro Expert

. Managed and overlooked over the PCB routing activities from the start

to finish which includes the PCB stack-up, routing constraint manager

etc..

. Performed Pre-routing signal integrity simulation using the Cadence

HyperLinx .

. Wrote the marketing requirement documents that includes the boards

functional block diagram using the MS Visio, Generate full project

development schedules using MS Project software

Tools: Cadence Allegro 16.3 HDL, Mentor Graphic Expedition 6.0, OrCAD

iStor Networks, Inc., IRVINE, CA. May/2006 -

Jan/2007

Principal Hardware Engineer

Design backplane controller for dual high availability 16 ports SAS/SATA

(Serial Attached SCSI) controller based on the Xilinx XC2V6000 FPGA. The

backplane controller supports PPC8241 CPU, dual DDR memory, 10/100/1G

Ethernet controller and 3GB high speed XAUI ports for inter controller

communication based on the Marvel M88X2040 PHY.

The FPGA is used to inject errors and simulate a drive disconnect between

the dual attached SAS controllers.

PEERLESS SYSTEM CORPORATION, El Segundo, CA. Jan/2004 -

Feb/2005

Hardware Principal Engineer

Responsible for designing ASIC validation board based on Xilinx XC2VP100

FPGA which includes two DDR SDRAM ports, dual processor interface (MIPS and

PPC750FX), PCI port (Device and Host mode), Intel LXT972A 10/100 MMI

interface, USP 2.0 PHY interface, NAND/NOR flash interface, DUART interface

etc. which includes PCB component placement, Gerber checking and testing.

Worked closely with ASIC team in driver selection, chip floor planning and

pin-out assignments.

Fully managed all design aspect from the start to finish which includes

project schedule and budgeting. Cadence OrCAD schematic capture tools were

used in the design.

Troika Networks, Inc., Westlake Village, CA November/2002-

Jan/2004

Manager, Board Engineering

Worked on next generation scalable 8 to 64 ports fibre channel storage

system design which includes the processor selection, back plan design,

high speed I/O interfaces and enclosure options.

Performed Troikas next generation ASIC HDL code validation using the

DiniGroup emulation controller which is based on the Xilinx Vertex2P FPGA.

Using MS project to put a detail controller development schedule form

initial design phase to start of production, which integrates and tracks

the ASIC development used in the controller.

Design the front-end 2GB fibre channel interface for a virtualized storage

router system using the Agilent Tachyon DX2 chip, which interfaces to the

Intel P64H2 PCI-X 133MHz dual hub.

Performed the high-speed signal integrity testing and system validation for

the 16-fibre channel ports storage router system which is based on Troikas

quad port 2GB fiber channel ASIC, CAM controller and Xilinx Vertex2 FPGA

using high speed differential probe scop.

Lincom Wireless, Los Angeles, CA Jan/2002-October/2002

Senior Hardware Engineering

Lead and managed the development of the mixed signals 345 balls LPGA

package substrate design for the 802.11 a/b Base Band comblink ASIC which

includes package selection, die/balls pin assignment, output driver

selection. The ASIC includes ARM processor, PCI /Card bus interface, SDRAM

interface, Flash ROM, EEPRM, 802.11 a/d modem, clock generation, Analog and

RFIC interface.

Performed ASIC primetime simulation timing analysis for the SDRAM memory

and PCI interface. Design and managed the development of the mixed signal

PCB controller for the 802.11 a/b base band comblink ASIC verification and

software development platform that includes ARM9 processor, CardBus/Mini-

PCI interface, SDRAM/Flash ROM interface, Xlinx CPLD, Analog and RFIC Front-

End interface port.

Design a four ports 802.11 a/b analog/digital hub controller board used for

air simulation in software development, which connects to four 802.11 a/b

base band combolink controllers using the I/Q interface ports using the

Xlinx XCR3256 CPLD.

OrCAD and ViewDraw schematic capture tools.

Troika Networks, Inc., Westlake Village, CA Aug/2000-Jan/2002

Manager, Hardware Development Engineering

Managed and lead a small hardware engineering design team in the

development and manufacturing of a more reliable 1 Gb/s Fiber Channel HBA

controllers based on the Intel GC80303 RISC processor and Troika,s HCA/TCA

ASIC utilizing the PCI/PCI-X host bus interface, this includes the

development of manufacturer Burn-In tester, safety/regulatory approvals and

electrical DVT (Design, Verify and Testing).

Designed and developed 2 Gb/s Fiber Channel HBA controllers based on the

Agilent DX2 dual fiber channel ASIC that supports 133MHz PCI-X host bus

interface.

Developed a detail Hardware development schedule and budget needed for the

development cycle.

Write HW functional specification and manufacturing test procedure for

every controller.

Worked very closely with the ASIC team in development of the next

generation 2 Gb/s HCA ASIC which includes output driver selection, package

selection and pin assignment.

Participated in the design and development of the next generation Internet

switch router using the Intel Pentium 4 processor and the Pluma's chipset,

which includes MCH that supports DDR memory, I/O CH and P64H2.

PEERLESS SYSTEM CORPORATION, El Segundo, CA. 4/1990 - Aug,

2000

Manager, Controller Development Engineer

Managed the Controller Development Engineering team for the last 2 years

which includes project assignments, detail hardware development schedule

and performance reviews.

Worked very close with the Sale/Marketing staff on writing new project

proposals for OEM customers, this includes an estimated Bill of Material,

hardware design development schedules and cost

Designed various Laser Printer controller boards for OEM customers based on

the Motorola PPC750/PP603 microprocessor and the Intel 80960CA which

includes on board SDRAM memory, CPLD, Flash ROM, USB port, 10/100 Base T

Ethernet port, PCMCIA port and Parallel Printer port etc. which includes

EMI testing and safety approvals.

QUOTRON SYSTEMS, El Segundo, CA. 7/1987 - 1/1990

Project Engineer.

Designed 32/24 ports communication controller used in multi-user super

computer systems, using the 68020 Microprocessor, 56 bits microsequencer

and 32 bit DMA.

Emulex Corporation, Costa Measea, CA 10/1985 -

7/1987

Hardware Design Engineer

Designed and troubleshot a 4/8 channel stands alone digital multiplexer

controller board using the 80186 Microprocessor, 2681DUART, 8530 SCC

controller and PLD's..

Education:

NORTHROP UNIVERSITY, Los Angels, California MSEE

RENSSELAER POLYTECHNIC INSTITUTE, Hartford, Connecticut

UNIVERSITY OF LJUBLJANA, Ljubljana, Slovenia BSEE

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