Engineer Electrical

Padmanabh Deshmukh

*** ************* *** * *********, NY 14623. ac1dfs@r.postjobfree.com Phone No :-+1-585-***-****

Objective: I am an Electrical Engineer currently seeking a full-time position in Analog Circuit Design, RF Circuit Design, Custom Layout Design (Available immediately)

Education

Master of Science- Electrical Engineering Year:2017

Rochester Institute of Technology, NY GPA:3.27/4

Relevant Courses: - Analog Devices, Microelectronics Fabrication, VLSI Process Modeling, CMOS Manufacturing, Fundamentals of MEMS, Thin Films, Engineering Analysis, Advance Engineering Mathematics.

Bachelor of Engineering- Electronics Engineering Year:2013

G.H. Raisoni College of Engineering CGPA:7.46/10

Relevant Courses: Network theory, Electronics Devices and Circuits, Digital Circuits, Power Electronics, Linear Electronics, Control Systems, Programming language C and Data Structure, Computer Architecture, Digital Communication, Microprocessors.

Technical Skills

Tools: Quartus II, ModelSim Altera, Silvaco Athena Atlas, MATLAB, SAP ERP, Informatica, Keil uversion 3.

Programming Language: C Language, Assembly Language, Verilog, VHDL, PL-SQL

Full Custom Chip Design: Cadence Virtuoso and Spectre, Mentor Graphics Pyxis.

Publication

Submitted Research paper in SOCC IEEE conference “A 0.36pJ/bit,17 Gbps OOK Receiver in 45-nm CMOS for inter and intra chip interconnects”

Research Projects

17Gb/s, 60GHz OOK Transceivers design in 45nm CMOS for Inter- and Intra-Chip wireless interconnect.

LNA:

The 2 stage LNA circuit is optimized to achieve gain of 27dB, 3dB bandwidth of 17GHz, Noise Figure of 2.8 dB, power consumption of 3.5mW at supply voltage of 1V.

Simulations to characterize LNA such as S-parameter, IIP3, Impedance matching were performed.

Envelope Detector:

Designed envelope detector consist of source degenerated differential amplifier at the input stage of envelope detector and two-stage buffer amplifier at the output.

The circuit is optimized to achieve gain of 16dB,power consumption of 1.3mW maximum data rate of 17Gb/s.

Power Amplifier:

The 2 stage Common Source Power Amplifier circuit is optimized to achieve gain of 17 dB and 3dB bandwidth of 15 GHz.

Simulations to characterize PA such as S-parameter, Power Added Efficiency, neutralization techniques were performed.

VCO

Designed 60GHz,NMOS cross coupled VCO, the phase noise of -103.4dBc/ Hz at an offset of 10MHz is achieved

The total power consumption of 1.1mW

Academic Projects

6 Bit pipeline ADC Design at 1 Volt Power Supply using 45nm PDK in Cadence

Designed 6 bit Flash ADC which exhibits DNL (differential nonlinearity) < 3.23mV, INL (Integral nonlinearity) < 3.30mV, 2.3mW power consumption Settling time < 90nsec using Cadence Virtuoso 45nm CMOS design kit for given specifications.

Designed circuits such as: Comparator, resistor ladder, 3 bit ADC, DAC, Unity Gain buffer using Op-Amp, Subtractor using Op-Amp was designed.

Comparator Design at 1 Volt Power Supply using 45nm PDK in Cadence

Designed a comparator and obtained Gain of 54dB, Hysteresis between 10m V and 20mV, Power dissipation was obtained 52uW and Propagation delays were under 6.2nsec.

Physical layout design for comparator using common centroid and inter digitization techniques are used.

Corner analysis and Monte Carlo Analysis were performed to study the variation in parameters.

Padmanabh Deshmukh

184 Crittenden way apt 1 Rochester, New York 14623 ac1dfs@r.postjobfree.com Phone No:-+1-585-***-****

Operational Amplifier at 1 Volt Power Supply using 45nm PDK in Cadence Virtuoso.

Schematic, Layout for the Operational Amplifier is designed in 45nm PDK in Cadence Virtuoso at 1 Volt power supply.

The total gain 55 dB with the Phase Margin of 54 degrees is obtained.

Circuit is simulated in different configuration to calculate PSRR, ICMR, OFFSET voltage, Output Rail to Rail Voltage.

DRC, LVS cleared, PVT analysis is performed.

β-Multiplier based constant Gm current Reference.

β-Multiplier based constant Gm current Reference current mirrors is implemented and verified using 45nm Technology (gpdk045) in Cadence Virtuoso.

Current of 25uA at 1Volt supply is achieved by calculating width and length of the transistor.

Sensitivity of current with the supply voltage and its sensitivity in open loop gain is studied and verified.

PVT analysis is performed.

BJT Diode based Bandgap voltage reference.

Bandgap Voltage reference is designed to have a temperature coefficient as low as 24ppm/ C in nominal case with including a start-up circuit using 45nm technology in cadence virtuoso.

The resistor values are chosen to cancel PTAT and CTAT and make the circuit temperature independent.

PMOS, NOR and NAND gate design, fabrication and electrical testing.

PMOS, NOR gates, NAND gate layouts are designed using Mentor graphics pyxis tool and the device fabricated on silicon n-type substrate.

Silvaco Athena and Atlas software are used to model device properties and material properties

The devices are fabricated using the standard processing steps such as Oxidation, Etching, Lithography, ion implantation, sputtering.

Electrical Testing is performed, the I-V characteristics are studied.

Effect of MOS Capacitance, CV characteristics, Threshold Voltage Adjustment in MOSFET devices using

Silvaco Atlas.

Simulation of MOS capacitance is performed on Silvaco Altas software.

CV characteristics of MOSFET with ideal and non-ideal threshold voltages were modeled and studied

Calculated non-ideal threshold voltage and simulated threshold voltage is verified.

The effect of flat band voltage, semiconductor potential, electric field and band bending in accumulation, depletion and inversion mode are studied.

Bulk FinFET Simulation using Silvaco Athena and Atlas Tools.

Process Steps involved in manufacturing Bulk FinFETs were modeled

Double Patterning, replacement metal gate, the effects of fin height, fin width is also studied and simulated.

Its device characteristics such as threshold voltage, Subthreshold swing and CV characteristics are simulated and studied using Silvaco Athena and Atlas tools.

Sub-Micron and Advance Sub-Micron CMOS Processing and Fabrication.

CMOS devices with channel lengths of 1.0 um and 0.5 um is fabricated using Sub-μ CMOS and ADV Sub-μ CMOS process technologies.

MESA tool (database for the process flow) is used while fabricating the devices.

Different process like RCA clean, Oxidation, Lithography, Etching, Ion Implantation, Sputtering are performed. Electrical testing is performed to verify the I-V characteristics, threshold voltage subthreshold swing, trans conductance.

Job Experience

Assistant System Engineer at TATA Consultancy Services

6 months work experience as an Assistant System Engineer at TATA Consultancy Services. Worked on Business Intelligence ETL tools like SAP ERP, Crystal Reports, Informatica, PL-SQL, Oracle 11g as a developer.

Contact this candidate