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Resume: Digital (ASIC/FPGA) engineer; Application Engineer; MSEE
To: abo2c3@r.postjobfree.com
Subject: Resume: Digital (ASIC/FPGA) engineer; Application Engineer; MSEE
From: Salah Kazi
Date: Sun, 20 Feb 2005 05:45:42 -0500
Message-id:
Attention:
Human resources manager / Engineering manager,
I am applying for the Electrical Engineer position in the field of
ASIC/FPGA design and verification, and Application engineering.
I have a Master's degree (MSEE) in Electrical Engineering and four
years of industry experience as an ASIC design engineer. I was
responsible for finding the cause of communication failure when the
DSP processor accesses Memory. I was also responsible for
generating ATPG patterns that passed functional test in Verilog.
I have worked on various stages of the design flow and have
performed functions such as RTL logic design using Verilog; design
verification; Dynamic timing analysis using TimeMill; ATPG using
Tetramax; FPGA design; PCB design.
Because of the market downturn, and the fact that I needed H1 visa
sponsorship, the consulting projects that I acquired were mainly in
web development and product marketing. These projects were customer
relations oriented and it benefited me because I can apply these new
skills in Application engineering jobs.
I am a Canadian resident and eligible for registration as a
Professional Engineer (P.Eng), willing to self-relocate
nationwide within Canada and USA. You can call me at 416-***-****
or 905-***-**** or email me at abo2c3@r.postjobfree.com
Sincerely,
Salahuddin (Salah) Kazi
84 Lemsford Drive, Markham, Ontario, L3S4H5 Canada
Tel: 416-***-**** (Cell), 905-***-**** (Home)
EFax: 806-***-****, Email: abo2c3@r.postjobfree.com
Web page: http://salahkazi.tripod.com/resume.htm
SUMMARY
MSEE, 4 years experience, worked extensively on dynamic timing
analysis using TimeMill, designed Remote I/O expander for I2C bus,
worked on ATPG. Experienced user of Verilog, TimeMill and Tetramax
OBJECTIVE
To work as an Electrical Engineer in the field of ASIC/FPGA design
and verification, and Application engineering
WORK EXPERIENCE
Consultant01/02 to present
Web designer, Atlanta GA
- Designed, developed, published and registered the website for americanimpex.com
VIG Computers, Atlanta GA
Computer technician
- Repaired, fixed and troubleshot computer systems and laptops
Seven Suns, Atlanta GA
Jobber, Product marketing
- Created more than 125 new accounts and became biggest jobber locally
Agere Systems, Atlanta, GA 05/00 to 01/02Functional design engineer
* Configured TimeMill and performed dynamic timing analysis and
solved issues on gate level netlist of DSP processor
* Configured PowerMill and performed power analysis
* Generated ATPG vectors using Tetramax that passed functional test
* Pushed Verilog RTL through the design flow using Epic tools Synopsys
* Verified Verilog cell library against Spice library using ATPG
test vectors
Fairchild Semiconductor, San Diego, CA 02/98 to 05/00
Digital Circuit design engineer
* Designed CMOS RTL logic of Remote 8-bit I/O expander for I2C bus
using Verilog HDL and verified design using Verilog-XL
* Verified the isophase mode of Video decoder and determined the
offset limits for the inputs and submitted report
* Designed error counter and entered schematic using ALTERA FPGA tools
* Edited PCB layout and schematic, and developed boot sequence for board
EDUCATION (MSEE)
Oklahoma State University, Stillwater, OK, USA
Master of Science, December 1997, Electrical Engineering
Osmania University, Hyderabad, India
Bachelor of Engineering, July 1995, Computer Science and Engineering
SKILLS
Application Software (UNIX Environment)
Verilog HDL, Viewlogic VHDL, Verilog-XL, TimeMill, PathMill,
EPIC tools suite by Synopsys, Tetramax, ALTERA MAX+II, HSPICE
Programming Languages
PERL, C, FORTRAN
ACCOMPLISHMENTS
* Designed a 32-bit SRAM memory unit at MOSFET transistor
level and tested read and write operations using SPICE
* Designed 32-bit Fast adder, Pipeline adder and 32-bit Barrel shifter
* Designed a RISC processor using VHDL and designed and tested 32-bit
ALU, and Central Processor Unit CPU for VLSI course project
* Designed 6 bit Binary Decoder with enable, 16-bit Register cell bus
and 16-bit Multi function register using VHDL, and Magic for layout
MISCELLANEOUS
* Eligible for registration as a Professional Engineer (P.Eng)
* Canadian resident
* Willing to self-relocate nationwide within Canada and USA
--
Salahuddin (Salah) Kazi
Tel: 416-***-**** (Cell), 905-***-**** (Home)
eFax: 806-***-****, Email: abo2c3@r.postjobfree.com
Web page: http://salahkazi.tripod.com/resume.htm
abo2c3@r.postjobfree.com
Salah Kazi (on-list)
Salah Kazi (off-list)
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