Design Engineer Quality

BRIAN ENGLES

PHYSICAL DESIGN ENGINEER ***-***-

*647

Austin, Texas

abmwb2@r.postjobfree.com

SUMMARY

Physical Design Engineer with over twelve years of physical design

experience. Team player willing to take on any task in order to meet

milestones and schedules. Able to innovate and solve problems while under

intense schedule pressure. Special expertise in:

Floorplan Timing Analysis Methodology/Scripting

Synthesis Noise Analysis Wire Bond

Place & Route DRC/LVS Flip Chip

Cadence SoC Encounter Synopsys Physical LEC

Compiler

PROFESSIONAL EXPERIENCE

Freescale/motorola, Austin, Texas 1993 - 2009

Physical Design Engineer, 1997 -

2009

Physical design of PowerPC microprocessors and embedded chip sets.

Responsible for chip level floor planning, and building of hierarchical

blocks from RTL to GDSII. Successfully completed critical path tasks as a

member of the design team for tapeout of 17 original PowerPC parts.

. Floorplanned PowerPC parts using a combination of Cadence and Freescale

tools. Completed initial feasibility studies and area planning based on

package type and architectural specifications. Placed hard and soft

blocks. Added power including multi-VDD. Completed clock-tree synthesis,

optimization, routing, and all other steps in the design flow. Delivered

high quality physical def files to block builders. Delivered chip level

netlist for extraction and timing. Completed DFM and delivered DRC-clean

tapeout-ready GDSII databases.

. Built hierarchical blocks from RTL to GDSII using Cadence SoC Encounter

that met all design requirements. Delivered DRC-clean tapeout-ready GDSII

databases.

. Reduced schedule time by using VPN remote access to keep CPU intensive

jobs running during nights and weekends.

. Completed chip level C4 design for an eight core Communications

Processor. Used pin list and package design rules to define C4 pitch, and

define placement of all C4 instances. Placed all power, ground and signal

C4 instances in the floorplan. Delivered a high quality C4 Map to package

design team.

Completed chip level wirebond design for a Dual Core Communications

Processor. Used pin list and package design rules to define initial

placement of all power, ground, signal and probe pads in the floorplan.

Teamed with package designer until all signal pads were successfully

routed in the package. Updated signal pad placements with the final

radial spreading coordinates generated by the Allegro IC Packaging tool.

Delivered coordinates for power, ground, signal and probe pads.

BRIAN ENGLES Page 2

Mask Designer, 1993 - 1997

Designed photomasks for PowerPC microprocessors, Process Development Test

Vehicles, and C4 bump technologies. Developed fracture algorithms for new

process technologies such as Trench Isolation and Optical Proximity

Correction.

. Co-inventor of Patent Title: Method For Minimizing Unwanted Metallization

In Periphery Die On A Multi-Sire Wafer This patent improved yield of die

around the periphery of a wafer by removing excess metal to prevent metal

peeling.

. Award for contribution to Trench Isolation process development.

. Designed reticles for .5, .35 and .25 micron process development test

vehicles.

. Developed methodology for bump mask design.

DuPont Photomasks, Round Rock, Texas 1989 - 1993

Technical Planning

Primary responsibility was to analyze customer data and technical

specifications for the preparation of ETEC data and EBEAM jobdecks for

exposure onto photomasks.

. Improved manufacturing efficiency by writing a program to show operators

exactly where on the photomask to measure critical dimensions.

. Authored documents for ISO 9000 Certification.

. Award for four consecutive years of perfect attendance.

. Quality Improvement Award April 1990.

. Quality Improvement Award August 1990.

EDUCATION

Coursework toward Master of Science Degree in Electrical Engineering

National Technical University, Fort Collins, Colorado

Bachelor of Science, Computer Science

Park College, Austin, Texas

PROFESSIONAL CERTIFICATIONS

CompTIA A+ - 2009 Edition

CompTIA Network+

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