Engineer Design

IMRAN A KHAN

E-mail: abms5i@r.postjobfree.com, Cell# 408-***-****, Home# 408-***-****

PROFILE: Ten years of PCB Layout Engineering career reflecting

outstanding

experience with High Speed/High Frequency Mixed signal,

RF/Microwave commercial,

prototypes, Evaluation, Rigid/Flex and ATE PCBs.

OBJECTIVE: Aspiring for a challenging and career oriented position in the

field of PCB Layout

Engineering.

WORK EXPERIENCE:

June 2008 - to date Hardware Engineering Layout Lead (PCB)

Freescale Semiconductor, USA (www.freescale.com)

Job Responsibilities:

PCB layout of mixed signal (Analog/Digital/RF), High Speed and high layer

count(up to 42), ATE(Verigy, Teradyne and Advantest testers),

Evaluation/Characterization PC Boards with micro vias (0.4 mm or less

BGAs).

Job Description

Interface with Engineers (Electrical and Mechanical) to understand PCB

design requirements. Create parts library (sch symbols and PCB footprints),

schematics (OrCad CIS and Concept HDL), component placement based on the

electrical and mechanical constraints; define Layer stack up, impedance

calculation for critical signals, design rules within Allegro Constraint

Manager based on design specs (differential pairs, cross talk, propagation

delay etc). Involved with Engineers in design simulations (PCB SI and Hyper

Lynx) to implement best design practices to minimize/eliminate EMI/ESD,

signal/Power integrity issues. Power/Ground planes, critical/non critical

signal routing. Conduct designs reviews with mechanical and electrical

engineers. Prepare artworks (RS 274X Gerbers, IPC356 NET LIST & ODB++) for

PCB fabrication and assembly drawings/documentations (BOM, XY data,

stencil/paste mask) for component assembly. Interface with Fab/Assembly

vendors to implement DFM/DFA friendly design constraints. Create SKILL

scripts to customize multiple functions in Allegro to shorten layout time.

Manage PCB design schedules and projects in US and overseas design

facilities. Help global PCB design transition from Mentor PADS to Allegro

16.xx. Conduct trainings and design review for layout team worldwide.

Streamline PCB layout process and develop design checklist and guidelines.

Submission of design documentation to Agile PDM system.

Oct 2006 - June 2008 Sr. Application Engineer (PCB)

Altanova Corp, San Jose, CA, USA (www.altanova1.com)

Job Responsibilities:

Designed and managed multiple mixed signal, High Speed digital and analog,

RF PCB, Blue Tooth & HDI design projects from start to finish for high

performance test boards, evaluation, probe cards and commercial boards

using Cadence Orcad and Allegro tools. Interface with customers to

understand design specs and develop design guidelines for layout team.

Mar 2006 - Oct 2006 Sr. PCB Layout Design Engineer

LeCroy Corporation, San Jose, CA, USA

(www.lecroy.com)

Job Responsibilities:

PCB layout of complex, mixed signal, High speed prototypes and production

boards to develop new test and measurement tools for leading edge

technologies such as SERDES, PCIe Gen1 & 2, Infiniband, Fiber Channel,

Ultra Wideband, SATA, SCSI, SAS, 1394, USB, Blue Tooth and others.

Sep. 2000 - Mar 2006 Sr. PCB Design Engineer

Nexlogic Technologies Inc. San Jose, CA, USA

(www.nexlogic.com)

Job Responsibilities:

PCB layout of complex, mixed signal, High speed prototypes and production

boards to develop new test and measurement tools for leading edge

technologies such as SERDES, PCIe Gen1 & 2, Infiniband, Fiber Channel,

Ultra Wideband, SATA, SCSI, SAS, 1394, USB, Blue Tooth and others. Have

designed boards for the major companies such as Applied Material, Salira

Systems, Agilent Tech, Philips Semi, WideBand, Gener8, Finisar, LumiLeds,

LSI Logic(Giga Blaze, 8.5 GHz), Finisar(PHY Chips), Leviton, Spansion LLC

(Agilent V3300, V4000/5000, Advantest T5371/T5376 DUT/Characterization

Brds.

Sep 1998. - Sep 2000 Hardware Engineer

Saztel Pvt Ltd (www.saztel.com)

Job Responsibilities:

Involved in R&D by using CAD tools in Hardware Engg Department, to install,

troubleshoot, test and repair at component/PCB level of multiple brand data

communication and IT products such as Motorola (Modems and Routers), PCOM

(Radio modems), Hyperlink (Access server and POS terminals), Cylink (Data

security) and 3Com (Switches and Hubs).

JOB RELATED SKILLS:

. Cadence Allegro 16.xx, Or Cad Capture 16.xx, Concept HDL, PCB

SI(Simulations)

. Mentor Graphics PADS Layout, Pads Router, Power Logic, DxDesigner,

Hyper Lynx

. PCAD 2006

. Downstream CAM350

. Polar Instruments 8000 Series

. AutoCad 200x & Solid Works

. Agile PDM database system

. Microsoft Word, Excel, Power point, Projects.

. Familiar with, Lead Free design and assembly, IPC Standards (IPC-2221,

2222, 610-A, 7351 D-325A, T-50), JEDEC, IEEE, EIAJ, ASME, PCB

fabrication processes, PCB materials (FR406/ 08, Rogers, NELCO4000-

13SI, GETEK, Polyimide etc).

. C++ and Assembly language

. Familiar with measurement instruments(spectrum analyzers, oscilloscope, signal generators etc)

TRAININGS/PUBLICATIONS/AWARDS:

. Speaker of Technical paper on the topic of Mixed-Signal PCB/Board

Design at PCB West conference, March, 2006, Santa Clara, USA.

. Completed short courses conducted at San Jose State University (2005)

on the topic of "Impact of RoHS on IC and MEMS Packaging" and

"Printed Circuit Board Manufacturing and Reliability"

. Author of 'Mixed Signal Design 'in FEB 2005, PCD magazine issue.

. Completed short course on Lead-Free RoHS compliancy Implementation

conducted by Kester University (2005).

. Received training for Cylink Security products from Singapore

conducted by Cylink U.S.A (Jan 1999)

. Trained in Private wire TCP/IP based software encryption from

Singapore conducted by Algorithmic Research Ltd. (AR) U.S.A.(Jan 1999)

. Received training for HP products at Hardware level conducted by HP

Singapore

(July 1999).

. Received two consecutive Gold Medals (1st and 2nd position) in

Institution of Electrical and Electronics Engineers (IEEEP) design

contests.

EDUCATION:

April. 1993 - Jul. 1998 M.U.ET.

Bachelors of Electronics Engineering with 3.8 GPA

(Four years degree)

Jan. 1995 - Dec. 1995 Petroman

Acquired a diploma in Computer Science

MEMBERSHIPS:

. Member of IEEE USA #41520546 and EMC society.

. Member IPC designer Council, Member# 1452225

Work Authorization:

Authorize to work for any employer in USA.

REFERENCES:

May be furnished upon request.

Contact this candidate