Design Engineer Quality Assurance

Henry Moy

**** ******* *****

Eagan, MN *****

612-***-****

ablp4e@r.postjobfree.com

SUMMARY

Design Engineer with ASIC design flow experience in the semiconductor

industry. Experienced in front-end design tasks on numerous ASIC chips and

testchips from Verilog netlist to final tapeout. Technical skills include

Verilog programming, netlist verification, netlist equivalence checking,

I/O ring specification and design, package bond wire and substrate design,

DFT insertion, STIL test vector development, synthesis of netlists using

Synopsys Design Compiler, and static timing analysis using Synopsys

PrimeTime.

EXPERIENCE

TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC., Bloomington, MN 2002-2009

Senior Design Engineer

Assisted customers in ASIC and testchip development from Verilog netlist to

final tapeout. Responsible for a wide range of front-end ASIC design flow

tasks on many projects. Acted as a group technical lead on I/O ring and

package design. Served as the primary interface between the customer's

logic design team, Toshiba's circuit design groups, and the place and route

engineers. Worked on signal integrity simulation and analysis for ASIC

designs using HSPICE.

. Wrote Verilog testbenches to setup, simulate, and verify PLL DFT tests

before insertion of these tests into a networking ASIC. Developed

STIL test vectors for these PLL DFT tests from Verilog simulation

waveforms to functionally test the PLL after fabrication of the ASIC.

. Wrote a script to automate membist test insertion into the memories of

an ASIC to reduce turnaround time. This script was used by fellow

engineers to insert membist test into other ASIC projects.

. Setup and ran equivalence checks between pre-DFT and post-DFT inserted

Verilog netlists using Cadence Encounter Conformal.

. Designed several dies for an I/O limited printer ASIC using Tri-Tier

I/O rings as part of a trade study to reduce the size of the die and

the overall cost by about one dollar per ASIC.

. Solved I/O ring placement problems involving SERDES, DDR2, LVDS, and

PLL IP to satisfy both customer I/O placement requests and the IP

designers' placement constraints in a printer ASIC. Designed the PBGA

package bond wires and substrate for this ASIC to meet bond wire and

substrate manufacturing constraints.

. Simulated critical timing path circuits in a networking ASIC using

HSPICE, which allowed more precise timing checks. Generated

schematics for these HSPICE simulations using Cadence Virtuoso

Schematic Editor to document the simulations.

. Generated and evaluated eye diagrams from HSPICE simulations to check

the signal integrity of SERDES transmitter and receiver circuit paths

through package models for customer ASIC designs. These eye diagrams

were used to verify customer lab results obtained from testing the

ASIC.

. Simulated the impedance of test board traces using the Time Domain

Response method, simulation models of the test board, and HSPICE to

determine if the test boards were manufactured correctly by a third

party source to meet Toshiba's specifications.

HENRY MOY 612-***-**** ( ablp4e@r.postjobfree.com

Page 2

. Calculated the total power dissipation of ASIC designs to ensure

designs did not exceed maximum package power dissipation

specifications.

. Performed IR drop and simultaneous switching analysis for ASIC designs

to determine if both these specifications were being met.

LSI LOGIC CORPORATION, Bloomington, MN 1998-2001

Design Engineer, Advanced and Custom Memory Group (2000-2001)

Responsible for memory integrated circuit design and analysis. Performed

schematic capture and design for memories including SRAMs, CAMs, and TLBs.

Verified the functionality and correctness of memories using HSPICE,

Timemill, Powermill, and Railmill.

. Analyzed issues such as charge sharing, leakage currents, power supply

noise, ground noise, input signal noise, and all possible fighting

conditions using HSPICE to size transistors in SRAM row decoder domino

NAND gates.

. Performed electromigration analysis of critical memory circuit paths

using HSPICE.

. Simulated the coupling capacitance between closely laid out metal

lines in HSPICE using capacitance pi models.

. Measured inverter switch points and transistor gate, area, perimeter,

and overlap capacitances for different transistor sizes and

technologies using HSPICE to examine inverter characteristics and

transistor capacitances in various technologies.

. Wrote a Perl script to automate the calculation of inverter switch

points and transistor capacitances using technology parameters and

transistor sizes as inputs.

Design Engineer, Library Development (1998-2000)

Worked on the quality assurance of library cells. Managed, generated, and

verified technical files and third party models for customers. Coordinated

schedules for the release of circuits.

. Defined library naming conventions and structures of release areas.

. Wrote and maintained C-shell scripts for the generation of technical

files and third party models.

. Solved timing and structural problems in circuits.

. Trained new engineers on generating the technical files and third

party models.

. Documented procedures and the syntax of the technical files.

EDUCATION

Master of Science, Electrical Engineering, University of Minnesota,

Minneapolis, MN

Bachelor of Science, Electrical Engineering, cum laude, University of

Minnesota, Minneapolis, MN

DESIGN TOOLS

Verilog, HSPICE, Synopsys PrimeTime, Synopsys Design Compiler, Cadence

Encounter Conformal, Cadence First Encounter, Cadence Encounter RTL

Compiler, Cadence Virtuoso Schematic Editor, Viewdraw, Awaves, Undertow,

Design Architect, Accusim, QuickSim II, MATLAB, Perl, C shell programming,

Timemill, Powermill, Railmill, UNIX, and Microsoft Applications.

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