Project Development
Resume:
Kavya Shah
Email- abljb2@r.postjobfree.com
Apt. No. - 1904
Round Rock, Texas
Zip code - 78664
Phone - 512-***-****/ 512-***-****
* *o make a positive impact in any field of activity, leading to
organizational and personal growth by creative application of my value
based conviction, job skills and professional dexterity.
3 Career Summary (Total Exp.- 4.8 years)
. Over 3 and half year experience as Member Technical Staff with HCL
Technologies Profile involves Front end Design and Verification, area of
expertise includes RTL Design, coding, Test Planning, Test Environment
Development, Testing, Code Coverage Analysis and development of GUI
Interfaces . She has good knowledge of Verilog, System Verilog, VHDL,
PERL and TCL language and has used various EDA tools like VCS,
Modelsim and NC-Verilog.
. Over 1 year experience as Technical Trainee (as part of M.Tech training
Programme) with HCL Technologies.
Educational Qualification
. M.Tech from Banasthali Vidhyapeeth, Banasthali with specialization in
VLSI Design(2004-06).
. B.TECH in Electronics and Communication from Galgotia's College of
Engineering & Technology Greater Noida affiliated to UPTECH University,
Lucknow.(2000-04)
Aggregate Marks: 75% in all semesters.
. Cleared JLPT(Japanese Language Proficiency Test) level 3.
Technical Skills Summary
Languages : Verilog, System Verilog, VHDL, PERL, Tk, C
Tools : NCSIM, VCS, Modelsim, DC, Simvision, Virsim,
DVE, IUS.
Documentation Tools : MS-Office
Operating Systems : Windows 98/2000, Linux
Work Experience
Organization: HCL Technologies
From 13th June, 2005 - 8th April, 2010
Designation: Member Technical staff
Project Details:
1. Verification of interrupt controller
Jan 10 - Mar 10
The project involves verification of a interrupt controller. Interrupt
controller (IC) is a device that is used to combine several sources of
interrupt onto one or more CPU lines, while allowing priority levels to be
assigned to its interrupt outputs. When the device has multiple interrupt
outputs to assert, it will assert them in the order of their relative
priority.
As a team member, I am responsible for:
. Study of Specification document.
. Identification test case scenarios.
. Development of test case list document.
. Writing test cases for the identified cases.
. Development of Monitor and Scoreboard.
. Execution of tests and reporting issues.
. Writing Functional coverage coverpoints and cross coverpoints.
. Analysis of functional coverage reports and writing more tests to
achieve 100% coverage.
A three member team was involved in verification of Interrupt Controller
using System Verilog based VMM methodology and VCS was used as compilation
and simulation tool.
2. Module level verification of SOC for high end Camera
Dec 08 - Nov 09
The project involves development of system on chip for a high resolution
camera chip for digital camera.
As a team member, I am responsible for:
. Study of Specification document.
. Development of test plan for modules for verification owned by me.
. Developing test cases and required environment settings for executing
tests.
. Execution of test cases and bug reporting for modules for verification
owned by me.
. Developing coverage setup for the chip and generating coverage
reports.
. Analysis of coverage reports and adding test cases to increase
coverage.
. Working with full chip team in debugging issues and helping in full
chip Verification.
. Running Gate level simulations for released netlist.
. Hands on Palladium, hardware accelerator by cadence.
. Modification in Environment for generating EVCD dumps for tester.
. Generating EVCD dumps for tester.
This project was handled at Client (Nethra Imaging Inc.) location in Santa
Clara, CA.
A twenty member team was involved in development and verification of SOC
using Verilog, C and IUS8.2.
3. Development of A8S Bridge (AXI to proprietary bus)
Mar 08 - Dec 08
The AXI-proprietary bus Bridge translates requests that appears on
AXI bus to proprietary bus requests and passes response from
proprietary bus back to AXI bus. The AXI-proprietary Bridge is to
be used in a SOC that have both AXI and proprietary bus based
systems and bridge will be used in the SOC to interface AXI bus
based system to SHwy bus based system. The bridge supports upto 18
read and 12 write outstanding requests.
As a team member, I am responsible for:
. Specification study.
. Developed Timing Charts for capturing latency of the
bridge at both the interfaces.
. Test case identification and test case coding.
. Functional coverage points identification and writing
functional coverage points.
. Integrated the Functional Coverage Module with the
Verification environment.
. Synthesis of the bridge rtl and Timing Analysis.
. Writing script for running regression and generation of
code coverage reports.
. Running regression and analyzing the reports generated
from regression run.
. Analysis of functional coverage and code coverage
reports.
A six member team was involved in development and verification of A8S
Bridge RTL on LINUX using Verilog, System Verilog, PERL and NCSIM.
2 4. Development of Memory Compiler
July ' 07 - Mar '08
The memory compiler was used for developing memory of a know depth using a
single SRAM cell. The compiler required a large set of generators for
extracting the memory netlist, memory models memory gds etc.
Each memory compiler is a set of various, parameterized generators. The
generators include:
1. Layout Generator : generates an array of custom, pitch-matched
leaf cells.
2. Schematic Generator & Netlister : extracts a netlist which can
be used for both LVS check and functional verification.
3. Function & Timing Model Generators : for gate level simulation,
dynamic/static timing analysis and synthesis
4. Symbol Generator : for schematic capture
5. Critical Path Generator & ETC : there are many special purpose
generators such as critical path generator used for both circuit
design and AC timing characterization.
As a team member, I am responsible for:
. Developed memory models for SRAM memory in VHDL and
Verilog.
. Developed Tailor to integrate a single SRAM cell into a
memory array.
. Developed GUI for memory compiler.
. Integration of tailor and memory models with the GUI.
A eight member team was involved in development and verification of Memory
Compiler on LINUX using PERL/Tk, Verilog, VHDL, Spice, Laker and Eldo.
5. Cross Coverage Analysis UART module
May '07 to Jul '07
The UART is a "Universal Asynchronous Receiver Transmitter" and is a piece
of hardware that translates data between parallel and serial interfaces.
The UART is the key component of the serial communications subsystem of a
computer. The UART takes bytes of data and transmits the individual bits in
a sequential fashion. At the destination, a second UART re-assembles the
bits into complete bytes.
As a team member, I am responsible for:
. Functional coverage points identification and writing
functional coverage points.
. Integrated the Functional Coverage Module with the
environment
. Generation of Functional coverage report.
. Analysis of Functional coverage report and
identification of new tests based on functional
coverage analysis.
. Achieving 100% functional coverage for the module.
A four member team was involved in verification of the UART RTL on LINUX
using System Verilog and VCS.
6. FPGA Codework Review
Jan '07 - May' 07
This project involved the review of the library components and FPGA's
provided by the client for review work.
As a team member, I am responsible for:
. Study of specification Documents.
. Review of the code and providing review comments.
. Updating the Review comments (if required), based on clients feedback
on the review comments.
A five member team was involved in Review of the library components and
FPGA's on LINUX using understanding of VHDL Language and preparing Review
reporting documents in MS-WORD.
7. SH-RS485 Verification
Aug '06 - Jan'07
This project involved adding an additional "RS485" mode in the existing
UART model and Verification of the same. The RS 485 mode was added to allow
some known delay before the start of serial transmission and after the end
of the transmission. These delay values were programmed into a programmable
register RS485 register. Depending on the mode selected the UART will work
in RS485 mode or non-RS485 mode. The Verification was done in both RS485
and non-RS485 mode.
As a team member, I am responsible for:
. Test planning and Identification of test cases to be
developed.
. Environment creation (developed BFM for the Serial
Interface).
. Coding of identified test cases.
. Execution of test cases and bug reporting.
. Verification of the DUT.
. Writing PERL scripts for regression and making changes
in test cases.
A two member team was involved in modifying the RTL for adding RS485 mode
and verification of the whole design after modification on LINUX using
Verilog, PERL and VCS.
8. Clock Tree Management Tool (CTMT) Development
Sep '05 - Aug. '06
This project involved the development of a Clock Tree Management Tool
(CTMT) that provides a graphical user interface (GUI) for viewing and
manipulating the clock tree. This Clock Tree Management Tool was developed
for the intended designers and users of clock tree.
As a team member, I am responsible for:
. Study of the implementation details of the tool and
Perl/tk.
. Coding for the Edit options required in the tool.
. Testing of the Tool and bug fixing.
. Managing bug report for the tool.
. Writing details of EDIT options in the User Manual.
. Adding new features in tool as requested by client.
. Updating the User Manual of the tool for new features
implemented.
A three member team was involved in development of the clock tree
management tool in LINUX using PERL/Tk.
9. ATSC Modulator Development
Jul. '05 - Sep. '05
This project involved development of an ATSC modulator which will do
channel coding and 8-VSB modulation for an ATSC transmission sub-system.
The ATSC modulator is one of the primary subsystem of a Digital television
subsystem. ATSC Modulator module implements Channel coder and 8-VSB
modulator module which adds required bits for error detection and
correction at receiver end, adds synchronization data at appropriate points
and final filter the resultant data stream to limit the bandwidth of
outgoing signal to 6 MHz.
As a team member, I am responsible for:
. Study of the Specification document.
. Developing individual blocks of the ATSC modulator (i.e.
Randomizer, Sync detector etc).
. Testing for the individual blocks of the ATSC modulator.
. Integrating the Environment.
A six member team was involved in development of the ATSC modulator on
LINUX using VHDL and Modelsim.
Academic Qualifications
. Passed class X with an aggregate of 86% (CBSE Board) from Cambridge
school NOIDA in the year 1998.
. Passed class XII with an aggregate of 87% (CBSE Board) from Cambridge
school NOIDA in the year 2000.
1 Roles & Responsibilities handled
. Understanding and executing Test Plan and deciding testing strategies.
. Performing functional, regression testing, coverage analysis etc.
. Provided mentoring to junior members of the team.
. Taken technical training sessions.
1 Strengths
. Optimist, positive thinker & ability to work under pressure.
. High energy levels and strong aptitude to learn.
Personal Details:
Name: Kavya Shah
Date of Birth: 12.12.1981
Father's name: Mr. R.K.Shah
Languages Known: English, Hindi, Japanese
Interests & Hobbies: Listening to Music
Passport No:
Date: Yours
faithfully
Place: Round Rock, Texas Kavya
Shah
*Employment status : EAD
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