Engineer Design

Bob Hickman

Digital FPGA Engineer

PROFESSIONAL SPECIALTIES

MICROPROCESSORs:

IBM405L, PowerQUICC-XPC860, IXP1200, 80386EX, 80C186, 80C188, and

Wintegra WIN747D2HBI.

FPGAs:

Xilinx: 3000, 4000E/XL, 5200, Spartan, SpartanXL, Spartan2, Spartan2E,

Spartan-3E, Virtex.

Actel: Act II, XL, 42MX, 54XL, ProASIC plus series, ProASIC3 FPGAs

Altera: Cyclone II, Cyclone III.

INTELLECTUAL PROPERTYs:

Xilinx: Microblaze, PowerPC 405.

Altera: ARM Cortex M1, C68000.

Actel: 8051.

ASICs:

POTS linecard ASIC for the Access Star DLC.

CPLDs:

Altera: 7000.

DSPs:

Texas Instruments: TMS320.

HDL TOOLs:

Modelsim, Synplicity and Xilinx/Altera/Actel Routers

Xilinx: ISE Design Suite 12.2 and Platform Studio XPS.

Altera: Quartus II v10.0 web edition.

HDL SCHOOL s :

VHDL: Cypress, Xilinx, Actel and Aldec.

VERILOG: Esperan and Xilinx.

PROFESSIONAL EXPERIENCE:

Digital FPGA Engineer Feb 09-Present

Brushfire Technologies, inc. Tulsa, Oklahoma

. Digital design of FPGA upgrades and new FPGAs on an as needed basis. Used

Altera Cyclone III, Xilinx, Spartan-3E and Actel ProASIC3 FPGAs. All FPGAs

were

designed using HDL(Verilog/VHDL), simulated with Modelsim and synthesized

using Synplify. Used Xilinx ISE for Spartan-3E for Microblaze processor.

Digital Hardware Engineer Jan 06-Feb 09

CarrierAccess Corp/Turin Networks/Force10 Networks Tulsa, Oklahoma

. Hardware Design of the Base card for the Axxius 800 product. Used the

Wintegra

WIN747D2HBI processor and Altera Cyclone II FPGA.

. Hardware Design of the Gigabit Ethernet card for the Axxius 800 product;

Used

Marvell 88E6095 Gigabit switch chip and Altera Cyclone II FPGA. All FPGAs

were

designed using HDL(Verilog/VHDL) editor, simulated with Modelsim and

synthesized

using Synplify.

Digital Hardware Engineer Oct 03- Dec05

Tucker Technologies, Inc. Tulsa, Oklahoma

. Hardware Design of the media access controller (MAC) FPGA for the Integra

product. Used Actel ProASIC plus Flash family. The MAC consisted of message

based communications at a 10 Mhz rate for down hole data logging (HDLC,

CRC,

Manchester, etc).

. Design of the BERT controller FPGA to test the high speed tool bus at

speed.

. Design of the Rate Adapter FPGA.

All FPGAs were designed using HDL(Verilog/VHDL), simulated with Modelsim

HDL editor and synthesized using Synplify.

Digital Hardware Engineer Aug 99- Oct 03

Carrier Access Corp. Tulsa, Ok

. Hardware Design of the CMG Router card for the Adit600/Axxius 800

product.

Used the IBM405L processor and Spartan II-E FPGA.

. Hardware Design of the P-Phone card FPGA for the Adit 600/Axxius 800

product.

Used SpartanII-E FPGA.

. Hardware Design of the Customer Media Gateway card for the Adit

600/Axxius

800 product. Used XPC860 microprocessor and SpartanII FPGA.

. Hardware Design of the VoIP Router card for the Adit 600 product. Used

XPC855T microprocessor and Spartan XL FPGA.

. Hardware Design of the Trunk Interface card for the Axxius 800 product.

. Hardware Design of the Alarm and Craft Interface card for the Axxius 800

product.

. Hardware Design of the Quad T1 Daughter card for the Axxius 800 product

All FPGAs were designed using HDL(Verilog/VHDL), simulated with Modelsim

HDL editor and synthesized using Synplify.

Digital Hardware Engineer June 89- July 99

Raytheon/Seiscor/Pulsecom Tulsa, Oklahoma

. Digital Design of the Terminal and Bank Control Processor cards

(TCP/BCP).

Designed FPGAs (Xilinx and Actel) for these processor cards.

. Digital design of the POTS ACCESS STAR linecard ASIC (AQLCAS)

. Design of the IDLC Extension card (TR303).

. Design of the STM1 Optical Interface Unit (OIU155) card. Used Xilinx

Virtex

series for the mapper designs.

. Major contributor to system architecture for the Access Star

International Digital

Loop carrier.

. Major contributor to system architecture for the RLC480 International

Digital

Loop Carrier system.

. Digital Design of the Bank Control Processor card. BCP used to process

calls from

240 line cardcage.

. Digital design of the POTS linecard ASIC (QLCAS).

. Design of the FPGA used for the dual channel ISDN card.

. Major contributor to system architecture for the Fibertraq2000 message

based

(TR303) Digital Loop Carrier system.

. Digital Design of the Line Shelf Processor card and the Main Processor

card

(CPU) for the Fibertraq system.

All FPGAs were designed using HDL(Verilog/VHDL), simulated with Modelsim

and

synthesized using Synplify.

Digital Hardware Engineer Oct 85- Jun 89

E-Systems, Inc. St Petersburg, Fl

. Digital Design of the Ethernet card for the (Telecom) Broad Band

Communications Bus (BCBII).

. Design of the control card for the Electronically Steerable Phased Array

(ESPA).

. Design of the Automatic test station for the KG84C key generator.

Digital Hardware Engineer Dec 79- Oct 85

Goodyear Aerospace Corp Phoenix, Az

. Digital Design of the CP39 Bi-static Radar System. Designed the Slant

Correlator

and High Density Tape Recorder Interface. Slant Correlator ordered targets

in

range and Doppler in consecutive radar slants.

. Digital design of airborne and ground station cards for the Sapphire

digital

Synthetic Aperture Radar system. Design of the 100 Mhz AD converter,

Highspeed PRF Buffer, Digital Target (CHIRP) generator, PTO Digital Filter,

Azimuth Autofocus, and Image Tape Recorder Interface cards

.

Digital Hardware Engineer Jul 74- Dec 79

American Electronics Labs Philadelphia, Pa

. Digital design of the Adaptive Signal Recognition and Direction

Identification

(ASRADI) AN/SQL-21 Electronic Counter Measure system. Designed the Threat

Processor and the Threat Parameter cards.

EDUCATION:

Master of Science, Electrical Engineering (MSEE)

Oklahoma State University

Bachelor of Science, Electrical Engineering (BSEE)

Oklahoma State University

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