Design Engineer

VISHAL DHAMI

***, * *** ******

Email: abihex@r.postjobfree.com

San Jose, CA-95110

Phone: 408-***-****

OBJECTIVE: Seeking a challenging position in ASIC/VLSI Design and Testing.

EDUCATION:

. MS (EE) San Jose State University, San Jose, CA

GPA: 3.50 December 2009

. BE (EC) C. U. Shah College of Engg. & Tech., Gujarat, India

GPA: 3.60 June 2006

SKILLS:

. Languages : VHDL, Verilog, System Verilog, C, Perl, Shell scripting,

8085/86 Assembly language, SQL.

. Tools : Cadence design environment (virtuoso schematic and

layout editor), Synopsys Design Tools (Core synthesis engine: Design

Compiler, Static timing analyzer), VCS Simulator, Xilinx ISE, Modelsim,

Cadence Encounter.

. O/S : Windows, UNIX, MS DOS.

. Lab Equipments: Logic analyzer, Digital oscilloscope, Spectrum

analyzer.

. Engg Concepts: IC Manufacturing Flow, BIST, Boundry Scan, Defect

Analysis, ATPG, Fault Coverage, Timing Analysis, Simulation and

synthesis, Test bench designing, Device physics & scaling, CMOS circuit

and logic design, Differential & Single stage op-amp.

WORK EXPERIENCE:

Design Engineer -Intern at Sahjanand Electronics, Ahmedabad, India

07/06-12/06

. Worked as an intern on the designing of Graphical LCD and Line Driver

with the resolution of 320*240. The hardware unit "Image Selection and

Display using Graphical LCD" was developed with Microcontroller 89V51RD2,

RS 232 and Graphical LCD.

. Key tasks were schematic design of architecture in OrCAD,

Programming of various graphical images in keil Compiler,

Testing of

design hierarchy, Soldering on PCB and loading of programs into

microcontroller.

RELATED COURSES:

Digital System Design And Synthesis

SOC Design and Verification

VLSI Design For Testability

Advanced Computer Architecture

ASIC CMOS Design

Advance Digital Design For DSP Comm

High Speed CMOS Circuit Design Mixed Signal Circuit Design

Semiconductor Device Physics

CURRICULUM PROJECTS & PAPERS:

Verilog HDL Coding, Gate level Synthesis and Place and Route tool Project:

PCIE protocol implementation

Verilog, ModelSim

. Designed two PCI Express compliant device modules that perform reads and

writes with the 32-bit variable size data payload.

. Implemented algorithm forms packets, which includes Header, TAG, sequence

number and data payload size.

. Data coherency was implemented using ACK/NACK protocol with reply buffer,

replay timer and ACK/NCK latency timer.

. Simulated and verified designed modules, capable generating error

correcting code and detecting Start of frame & End of frame.

Look through Cache memory subsystem

Verilog, ModelSim

. Designed 2-way set associative look-through cache system attached with 32

bit processor and 32K physical memory

. Implemented snooping algorithm in the cache controller to observe other

bus master access to main memory

. Simulated various read and write cycles from virtual memory using paging

scheme and LRU algorithm

A 4 by 4 Keypad Scanner & Encoder

Verilog,

VCS, Synopsys Synthesizer

. Built and integrated four different module using Verilog HDL including

FSM to encode the key pressed.

. Functional simulation and verification was performed in VCS.

. Synthesized in various libraries, optimized with particular attributes

and constrains and also did timing, area and power trade off analysis.

. Layout was generated by using Gate level net list which was generated by

Synopsys Design Compiler given as input file to Cadence encounter place

and route tool.

4x4 MAC design for 2C fractional format

Verilog,

Xilinx ISE 10.1, Multiplier core

. MAC engine takes two 4-bits 2C fractional number, multiplies the two,

and outputs the

. 8 bits product. Rounding logic rounds 8 bits to 4 bits product.

. MAC engine accumulates the product to the 4 bit register with saturation

logic.

. Developed logic takes care of signed number, rounding and saturation

logic.

. Verification of design was done by test pattern provided by professor.

16x16 Signed array divider design for 2c fractional format

Verilog, ModelSim

. Divider logic takes two 16 bits 2c fractional numbers and gives output

of 16 bits.

. Developed RTL code which takes care for signed number and saturation

logic.

. Verification of RTL code was done using test patterns provided by

professor.

Circuit and Custom Layout Design Projects:

High speed 32-bit Program Counter using Dynamic Domino logic

(IBM 0.13 u, 4 GHz clock frequency, 1.3 V supply)

. Designed 32 bit Program Counter using IBM 0.13u technology with Jump,

Stack and Hold functionality which runs at 4 GHz.

. Project involves Transistor sizing with Dynsize software, Schematic and

layout in cadence Virtuoso tool

. Challenges are transistor sizing, Debugging, timing analysis, Floor

planning, Layout and Verify DRC/LVS errors.

6 Bit Digital to Analog converter

(TSMC 0.24 u, 4 GHz clock frequency, 2.4

V supply)

. Designed 6 bit thermometer coded DAC in cadence tool using TSMC 0.24

technology which runs at 4GHz.

. Project involves thermometer code design using dynamic domino logic,

register and current reference design, drawing schematic, transistor

sizing, simulation, Floor planning, debugging, verify DRC/LVS and Layout

in cadence virtuoso tool and post extraction.

Built in Self Test (BIST) for Integrated Circuits

. Presented unpublished research paper on BIST for integrated circuits

design. It mainly focused on an approach to test Integrated

Circuits using BIST to reduce cost, power consumption and improve

fault coverage.

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