Engineer Design

Xin Zhang

*** ******** *****

Allen, TX *****

Email: abh6zo@r.postjobfree.com

Phone: 972-***-****

Experience Highlight:

( 10-year experience in high performance ASIC physical design.

Accomplished IC engineer with extensive experience in design

methodology, floorplan, clock tree synthesis, place and route,

signal integrity, static timing analysis and timing closure,

design for manufacturing, power, and DRC/LVS. Proven ability

to successfully implement complex ASIC design. International

assignment (expatriate) experience.

( 4-year experience in logic design, had worked on PCI

North Bridge design for high performance

integrated processor, bus interface unit

for 586-like and 486-like embedded micro-controller.

( 1-year experience in clock distribution network design

for a high performance processor design.

( 1-year experience in custom layout for a processor

design.

Experience:

05/03 - Current Lead Design Engineer

Texas Instruments ASIC, Dallas, TX

( Member of ASIC top level implementation team

responsible for physical design and timing

closure of large and complex ASIC design.

Have successfully taped out 10 designs which

included 0.13um, 90nm, 65nm and 45nm

technology. Roles have consisted of design lead, top

level physical designer, SOC subsystem

physical design lead and the lead STA engineer

respectively. The following are the areas

that I had extensive working experience on:

- Customer interface, resource allocation, schedule

development, risk assessments and making

sure the project is on track (as design lead)..

- Design planning, design partition and top level floorplan (as

design lead/top level designer)..

- Top level placement (as top level designer).

- Clock implementation for top level (as top level designer).

- Top level routing (as top level designer).

- Full chip STA and timing closure (as top level designer).

- Wrote a simple top level timing budgeting script for a

processor design (as STA lead).

- Physical integration of IPs for the SOC design (as SOC design

lead).

- Block level floorplan with RAM and various IPs for SOC

subsystem.

- Clock tree implementation for the complex clocking system of

a SOC subsystem.

- Block level place and route, STA and timing closure for the

SOC subsystem.

- Worked closely with different IP owners and designers to

develop the constraints for the SOC.

( Had 1+ year of expatriate experience. Led a

very complex SOC design for a leading China

telecommunication company.

- Customer interface. Worked very closely with customer and

help them quickly to transition to

TI technology and to use TI technology smoothly. Understood

the customer needs and

issues and fed them into proper TI teams for resolution.

Arrange TI internal resource to work on

customer issues/needs promptly.

- Managed/allocated the local design resource and the external

contractor resource for the design.

- Making sure the project is on-track. Developed the project

schedule.

- Provided technical advice on different aspects of the design

to the local China design center

engineer. Mentor and training the local engineer.

09/99 - 04/03 Advisory Engineer

IBM Central ASIC Design Center, Dallas, TX

. Worked as Front End Designer in ASIC design. Had successfully

taped out 9 designs. Three of them were designs using IBM's

0.10um, copper technology. One of them has about 1.6 million

place-able objects and has clock frequency of 500 MHz.

- Keeping schedule. Coordination of IBM technical

resource on the design

- Top-level IO, JTAG insertion using IBM internal

tool (IOSpecDFT), DFT synthesis.

- Functional clocks and test clocks synthesis.

- Main Technical interface with Customer. Worked

with customer on various design tasks, such

as power estimation, timing constraint

development for IBM's static timing tool, floorplan, etc.

Provided technical consultant to customer

on IBM technology related issue.

- Worked with Physical Designer to balance all the clock trees

and fix all the electrical violations in the clock tree.

- Static timing analysis.

- Responsible for the timing closure of the design.

Analyzed and fixed timing problems in all timing corner

including the process variation (LCD model). Analyzed and fixed timing

Problems caused by cross coupling.

02/98 - 09/99 Sr. VLSI Design Engineer/Staff Engineer

Cyrix/National Semiconductor Co., Richardson, TX

01/99 - 09/99 . Worked on Cyrix's Gobi chip (500MHz MXI core + Socket 370

interface + L2 Cache) design.

. Responsible for the Cyrix's Gobi chip clock

distribution network design.

- Design and implemented all the clock distribution networks (H-

tree network design for global clocks and mesh network for

local clocks).

- Implemented all the clock buffers (Semi-Custom design).

- Extracted, analyzed and balanced all the clock trees. The

clock skew for all the Gobi clocks met

the goal with the overall skew of 150ps.

02/98 - 12/98 . Designer of MXI PCI Host Bridge design for Cyrix's 500 MHz

MXI chip. The primary function of

the PCI Host Bridge is to manage and translate

bus transactions between the internal CPU core bus

and the external PCI Bus.

- Supporting MXI PCI Host Bridge design. Made

function changes, added new functions and fixed bugs in PCI

RTL.

- Synthesis and optimized the PCI design.

- Placed and routed the PCI block.

- Timing closure for PCI.

- Ran Formal verification (Chrysalis) for any re-

synthesis, function changes and bug fixes.

- Debug all reported problems related to PCI from System Lab,

silicon debug and regression test,

etc. Wrote new stand-alone tests for any bug fixes.

11/95 - 01/98 Sr. Design Engineer / Design Engineer

National Semiconductor Co., Arlington, TX

. Designer of Bus Interface Unit for two National's microcontroller

designs: the National's

Embedded 32-bit 586-class Microcontroller

design and National's 32-bit 486-class Embedded

System (NS486-SXL) design. Bus Interface Unit

is the central interface unit between processor's

Local Bus and VESA VL-Bus, ISA bus, ROM/Flash

chip selects, external and internal peripheral,

and Bus Master Logic in NS486-SXL.

- Spec and micro-architecture of BIU (.the

Embedded 32-bit 586-class Microcontroller design)

- HDL coding of BIU and Bus Master Logic (BML)

using verilog.

- Synthesized and optimized BIU and BML.

- Developed the test vectors for BIU and BML.

- Verification and simulation of BIU and BML.

- Fixed critical paths in BIU and BML.

07/94 - 11/95 Product Development Engineer

Advanced Micro Devices Inc., Austin, TX

. Worked on AMD's K5 project. Fixed timing problems,

spice simulation, design checks, and

custom layout of microprocessor blocks and

padring.

Education: Texas Tech University, Lubbock, Texas

M.S. in Electrical Engineering, August, 1994

M.S. in Physics, November, 1993

GPA: 4.0/4.0

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