| Resume alert | Resumes 91 - 100 of 450 |
Engineering Electrical
San Jose, CA
... Skill Sets: Languages: C, Python, C++, Verilog, Shell Scripting. Design & Hands-On Experience: Git, GitHub, Beagle Bone Black, Arduino Uno, Raspberry Pi 3, ESP8266, OpenMP, OpenACC, OpenCL, MPI, Tensorflow, Keras, Home Automation, Microsoft Office. ... - 2018 May 18
... Skill Sets: Languages: C, Python, C++, Verilog, Shell Scripting. Design & Hands-On Experience: Git, GitHub, Beagle Bone Black, Arduino Uno, Raspberry Pi 3, ESP8266, OpenMP, OpenACC, OpenCL, MPI, Tensorflow, Keras, Home Automation, Microsoft Office. ... - 2018 May 18
Software Engineer State University
San Jose, CA
... RS-485 • Matlab, Ada, Satellite Tool Kit (STK), SCL, and SCS-21/STSS • PERL, Python, TCL/TK, Unix shell (TCSH/CSH) scripting, and Verilog • GUI development using XML, X-Windows/Motif, MFC, Visual Studio C++/C#, Qt/QML, and Kinesix Sammi • Clearcase ... - 2018 Apr 22
... RS-485 • Matlab, Ada, Satellite Tool Kit (STK), SCL, and SCS-21/STSS • PERL, Python, TCL/TK, Unix shell (TCSH/CSH) scripting, and Verilog • GUI development using XML, X-Windows/Motif, MFC, Visual Studio C++/C#, Qt/QML, and Kinesix Sammi • Clearcase ... - 2018 Apr 22
Design Electrical Engineering
Santa Clara, CA
... RELATED SKILLS • Computer: Cadence Virtuoso, SpectreRF, ADS, Momentum, Altium, Matlab, Verilog HDL, Python, C lan- guage, MySQL • Hardware Lab: VNA, Spectrum Analyzer, Oscilloscope, Waveform Generator • Presentation skills: office softwares ... - 2018 Mar 29
... RELATED SKILLS • Computer: Cadence Virtuoso, SpectreRF, ADS, Momentum, Altium, Matlab, Verilog HDL, Python, C lan- guage, MySQL • Hardware Lab: VNA, Spectrum Analyzer, Oscilloscope, Waveform Generator • Presentation skills: office softwares ... - 2018 Mar 29
Design Electrical Engineering
San Jose, CA
... Digital Delay Locked Loop – Xilinx Vivado, Verilog Implemented an all-digital Delay Locked Loop on Be Micro Max10 FPGA Evaluation board. Perfect lock-in scenarios achieved up to a frequency of 150 MHz Image Filtering – C, CUDA Implemented Sobel, ... - 2018 Mar 29
... Digital Delay Locked Loop – Xilinx Vivado, Verilog Implemented an all-digital Delay Locked Loop on Be Micro Max10 FPGA Evaluation board. Perfect lock-in scenarios achieved up to a frequency of 150 MHz Image Filtering – C, CUDA Implemented Sobel, ... - 2018 Mar 29
Firmware Validation, Automation and Test Engineer
San Jose, CA
... TECHNICAL SKILLS: Programming Languages: C, Python, Verilog Tools: Teledyne LeCroy, QTP, Selenium, HP Quality Center, GitHub, JIRA, Protocol Analyzer Technologies: NAND, 3D NAND, CMOS, ASIC, FPGA, WIFI, USB, Bluetooth Storage Protocols: SCSI, SAS, ... - 2018 Mar 27
... TECHNICAL SKILLS: Programming Languages: C, Python, Verilog Tools: Teledyne LeCroy, QTP, Selenium, HP Quality Center, GitHub, JIRA, Protocol Analyzer Technologies: NAND, 3D NAND, CMOS, ASIC, FPGA, WIFI, USB, Bluetooth Storage Protocols: SCSI, SAS, ... - 2018 Mar 27
Software QA Manager
Newark, CA, 94560
... Networking tools: Wireshark, tcpdump Simulation & Circuit tools: LTSpice, Pspice Hardware languages & tools: VHDL, Verilog, Xilinx ISE, Quartus II Others: Agile, Scrum Experience Software QA Manager/QA Technical Lead Vertical Communications, Inc. ... - 2018 Mar 27
... Networking tools: Wireshark, tcpdump Simulation & Circuit tools: LTSpice, Pspice Hardware languages & tools: VHDL, Verilog, Xilinx ISE, Quartus II Others: Agile, Scrum Experience Software QA Manager/QA Technical Lead Vertical Communications, Inc. ... - 2018 Mar 27
Engineer Hardware Design
San Jose, CA
... ● Software: Python, Verilog, Corelis, JTAG, LabView. ● Database tools: Agile, Arena. Recent Experience 2006-2017 Santa Clara, CA Senior Hardware Engineer ● Designed a new generation of low cost trusted IP Network to serve the South Korean Market ... - 2018 Mar 20
... ● Software: Python, Verilog, Corelis, JTAG, LabView. ● Database tools: Agile, Arena. Recent Experience 2006-2017 Santa Clara, CA Senior Hardware Engineer ● Designed a new generation of low cost trusted IP Network to serve the South Korean Market ... - 2018 Mar 20
Design Engineer
San Jose, CA
... EDUCATION MS, San Jose State University, Electrical Engineering GPA: 3.56/4 Jan 2016 – Dec 2017 Special Topics in Digital Systems(UVM), ASIC CMOS Design, SOC Design and Verification with System Verilog, Digital Design for DSP/ Communication, ... - 2018 Mar 13
... EDUCATION MS, San Jose State University, Electrical Engineering GPA: 3.56/4 Jan 2016 – Dec 2017 Special Topics in Digital Systems(UVM), ASIC CMOS Design, SOC Design and Verification with System Verilog, Digital Design for DSP/ Communication, ... - 2018 Mar 13
Design Engineer
San Jose, CA
... MIPS CPU Design New York University January 2016 – May 2016 • Designed an RTL based single cycle 32 bit MIPS processor and implemented it using Verilog, on Nexys 4 DDR FPGA. • Implemented 12 instructions and techniques which would enable the Simple ... - 2018 Mar 08
... MIPS CPU Design New York University January 2016 – May 2016 • Designed an RTL based single cycle 32 bit MIPS processor and implemented it using Verilog, on Nexys 4 DDR FPGA. • Implemented 12 instructions and techniques which would enable the Simple ... - 2018 Mar 08
Electrical Engineer State University
Union City, CA
... Technical Engineering Expertise Programming Languages: C, C++, Verilog, PHYTON, MATLAB, MATHCAD, XILINX ISE Design (Verilog) Instrumentation and Equipment: Oscilloscope, Function Generators, Digital Multi-Meter, 3D Printers, Electric Soldering Iron, ... - 2018 Mar 01
... Technical Engineering Expertise Programming Languages: C, C++, Verilog, PHYTON, MATLAB, MATHCAD, XILINX ISE Design (Verilog) Instrumentation and Equipment: Oscilloscope, Function Generators, Digital Multi-Meter, 3D Printers, Electric Soldering Iron, ... - 2018 Mar 01