| Resume alert | Resumes 101 - 110 of 194 |
Design Electrical Engineering
Fullerton, CA
... India GPA- 3.5 Technical Skills: Language: VHDL, Verilog, System Verilog, SystemC, Perl EDA Tools: Cadence (Virtuoso schematic/Layout editing), Microwind, Chip scope, Modelsim, Xilinx –vivado, Xilinx ISE, Synopsys, MATLAB, LT-Spice, DSCH, Hspice. ... - 2016 Jun 07
... India GPA- 3.5 Technical Skills: Language: VHDL, Verilog, System Verilog, SystemC, Perl EDA Tools: Cadence (Virtuoso schematic/Layout editing), Microwind, Chip scope, Modelsim, Xilinx –vivado, Xilinx ISE, Synopsys, MATLAB, LT-Spice, DSCH, Hspice. ... - 2016 Jun 07
Design Project
Lakewood, CA
... Computer Architecture Designed a 32-bit MIPS-based CPU in structural Verilog. Filter Design Analysis and (software) design of Analog and Digital filters. Circuit Network Analysis R, RC, RL, RLC circuits; Diodes, Transistors (BJT, JFET, MOSFET); ... - 2016 May 14
... Computer Architecture Designed a 32-bit MIPS-based CPU in structural Verilog. Filter Design Analysis and (software) design of Analog and Digital filters. Circuit Network Analysis R, RC, RL, RLC circuits; Diodes, Transistors (BJT, JFET, MOSFET); ... - 2016 May 14
Electrical Engineering
Los Angeles, CA
... Verilog and State Machine University of California, Los Angeles, CA Fall 2015 • Wrote in Verilog for state machine and wrote test bench to test the result. Noise Filtering and Object Segmentation University of Washington, Seattle, WA September ... - 2016 May 04
... Verilog and State Machine University of California, Los Angeles, CA Fall 2015 • Wrote in Verilog for state machine and wrote test bench to test the result. Noise Filtering and Object Segmentation University of Washington, Seattle, WA September ... - 2016 May 04
Electrical Engineering Design
Los Angeles, CA
... India July 2013 Bachelor of Engineering, Electronics Engineering GPA: 71.5/100 TECHNICAL SKILLS Programming Languages: Verilog, C, Perl, Python, VHDL Tools: ModelSim, Cadence Virtuoso Layout Editor, NCSim, SoC Encounter, Synopsys Design Compiler, ... - 2016 Apr 29
... India July 2013 Bachelor of Engineering, Electronics Engineering GPA: 71.5/100 TECHNICAL SKILLS Programming Languages: Verilog, C, Perl, Python, VHDL Tools: ModelSim, Cadence Virtuoso Layout Editor, NCSim, SoC Encounter, Synopsys Design Compiler, ... - 2016 Apr 29
Engineer Design
Los Angeles, CA
... Tools: Behavioral Simulation - Synopsys VCS, NCVerilog, Icarus Verilog, ModelSim, Canalyzer. Synthesis - Synopsys Design Compiler Gate Level Simulation - NCSim FPGA tools - Xilinx ISE and Vivado, Altera Quartus II Place & Route - Cadence Encounter ... - 2016 Apr 24
... Tools: Behavioral Simulation - Synopsys VCS, NCVerilog, Icarus Verilog, ModelSim, Canalyzer. Synthesis - Synopsys Design Compiler Gate Level Simulation - NCSim FPGA tools - Xilinx ISE and Vivado, Altera Quartus II Place & Route - Cadence Encounter ... - 2016 Apr 24
Test Cases Professional Experience
Orange, CA
... Tools: Eclipse, Google Map, Developer tools, HP tools, Chef GUI Text Editors: Notepad++, Sublime Software: Matlab, Vhdl, Verilog, Keil Other tools: Jenkins, Hudson, Github, Git, Svn, Aws PROFESSIONAL EXPERIENCE Splan.inc, Fremont, CA April 2015 – ... - 2016 Mar 01
... Tools: Eclipse, Google Map, Developer tools, HP tools, Chef GUI Text Editors: Notepad++, Sublime Software: Matlab, Vhdl, Verilog, Keil Other tools: Jenkins, Hudson, Github, Git, Svn, Aws PROFESSIONAL EXPERIENCE Splan.inc, Fremont, CA April 2015 – ... - 2016 Mar 01
Java Developer Computer Engineering
Los Angeles, CA
... + Developed a technical manual (chip specifications) for a SOC design (programmed in Verilog). The chip was composed of an 8-bit microcontroller (PicoBlaze) and UART interface which was developed and tested using the Nexys 2 FPGA board. The software ... - 2016 Feb 15
... + Developed a technical manual (chip specifications) for a SOC design (programmed in Verilog). The chip was composed of an 8-bit microcontroller (PicoBlaze) and UART interface which was developed and tested using the Nexys 2 FPGA board. The software ... - 2016 Feb 15
Engineer Electrical Engineering
Irvine, CA
... Line Diagrams using SKM Power Tools Skills: Good understanding of SKM Power Tools, PowerWorld, ETAP and LabVIEW C++ programming, Verilog and assembly language MATLAB Good understanding of Unix and Linux OS PSPICE simulations with Digital and Analog ... - 2015 Dec 28
... Line Diagrams using SKM Power Tools Skills: Good understanding of SKM Power Tools, PowerWorld, ETAP and LabVIEW C++ programming, Verilog and assembly language MATLAB Good understanding of Unix and Linux OS PSPICE simulations with Digital and Analog ... - 2015 Dec 28
Manager Engineer
Irvine, CA
... * Awards/ Publications: 1 issued and 2 pending patents in iStor Networks SKILLS: FPGA Design: - Altera, Xilinx VHDL & Verilog for logic entry: - ModelTech, Synplicity, MaxPlus Firmware Design: - C++, C# ASIC Design - LSI Logic Tools, Toshiba ... - 2015 Dec 11
... * Awards/ Publications: 1 issued and 2 pending patents in iStor Networks SKILLS: FPGA Design: - Altera, Xilinx VHDL & Verilog for logic entry: - ModelTech, Synplicity, MaxPlus Firmware Design: - C++, C# ASIC Design - LSI Logic Tools, Toshiba ... - 2015 Dec 11
Project Design
Orange, CA
... Technical strengths: Proficient with RTL design using Verilog HDL and System Level Design as well as System Verilog and Open Verification Methodology (OVM). FPGA-based design on a Network on Chip communication channel research project. Good ... - 2015 Dec 08
... Technical strengths: Proficient with RTL design using Verilog HDL and System Level Design as well as System Verilog and Open Verification Methodology (OVM). FPGA-based design on a Network on Chip communication channel research project. Good ... - 2015 Dec 08