| Job alert | Jobs 111 - 120 of 164 |
Senior Design Verification Engineer
eInfochips (An Arrow Company)
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Bengaluru, Karnataka, India
... with hands on experience, mentoring, client communication / interactions, in-depth technical reviews, and close tracking of technical as well as management aspect ESSENTIAL SKILLS & EXPERIENCE • At-least 4 years of experience in System Verilog HVL. ... - Jun 18
Physical Design and Machine Learning Engineer, Silicon
Google
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Bengaluru, Karnataka, India
... Knowledge of computer architecture and Verilog/SystemVerilog. Knowledge of circuit design, device physics, and sub-micron technology. Knowledge of algorithms and data structures. About the job Our computational challenges are so big, complex and ... - Jun 21
Senior ASIC Design Verification Engineer
eInfochips (An Arrow Company)
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Bengaluru, Karnataka, India
... with hands on experience, mentoring, client communication / interactions, in-depth technical reviews, and close tracking of technical as well as management aspect ESSENTIAL SKILLS & EXPERIENCE · At-least 4 years of experience in System Verilog HVL. ... - Jun 18
R&D Engineering, Staff Engineer
Synopsys
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Sadduguntepalya, Karnataka, 560029, India
... · Good knowledge of Verilog and VHDL HDL/RTL languages and digital design. UPF knowledge is preferred. · Experience with tools such as Coverity, valgrind etc. · Working knowledge of FPGA prototyping tools and flows. Business Title (Title for Job ... - Jun 21
ASIC Digital Design, Staff Engineer
Synopsys
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Sadduguntepalya, Karnataka, 560029, India
... The TE must have used methodologies such as UVM, OVM Test Planning, Coverage Planning, Assertion Planning Hands on experience with System Verilog coding and Simulation tools; Deep Knowledge of OOPs Concepts Experience with Perforce or similar ... - Jun 19
CAD Methodology Engineer, Front-End
Google
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Bengaluru, Karnataka, India
... experience 3 years of experience with development projects in VLSI Experience in RTL design, verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation Preferred qualifications: Master’s degree in Computer ... - Jun 09
ASIC Digital Design, Staff Engineer
Synopsys
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Sadduguntepalya, Karnataka, 560029, India
... The TE must have used methodologies such as UVM, OVM Test Planning, Coverage Planning, Assertion Planning Hands on experience with System Verilog coding and Simulation tools; Deep Knowledge of OOPs Concepts Experience with Perforce or similar ... - Jun 19
Applications Engineering, Engineer
Synopsys
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Sadduguntepalya, Karnataka, 560029, India
... Must have very good understanding of the issues involved in ASIC to FPGA RTL preparation Experience with design, verification, post silicon bring-up and validation Knowledge of Digital Design, VHDL/Verilog/SystemVerilog, Synthesis, Simulation and ... - Jun 26
Verification Manager
Mulya Technologies
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Bengaluru, Karnataka, India
... Experience with RTL Debugging, Score-Board/Assertion Development and Code Coverage Analysis Sound knowledge of System Verilog and UVM Methodology The position requires good Written & Verbal Communication Skills Strong Commitment and ability to ... - Jun 25
R&D Engineering, Sr Engineer
Synopsys
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Sadduguntepalya, Karnataka, 560029, India
... • Familiarity with Verilog/VHDL RTL level designs, timing constrains, static timing analysis. • Working knowledge of FPGA design tools and flows is a plus. Business Title (Title for Job Posting) Sr Engineer Job Category Engineering Job Subcategory R ... - Jun 14