Principal Engineer, RTL ASIC Design (PCIe/ CXL)

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your ImpactThe Custom and Compute Solutions Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up.

What You Can Expect

Define the memory sub system architecture, micro-architecture and register specification for highly complex SoCs. Drive and participate in specification writeup

Conduct detailed performance, architectural and design requirement reviews with cross-functional teams, IP Vendors and customers

Implement a specification using RTL coding techniques and best practices

Work with third party vendors to define customization requirements of third party IPs (controller, PHY, etc.)

Work with the physical design teams, reviewing and providing guidance in floorplanning, power analysis, synthesis and timing signoff.

Work with the verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip simulation and emulation, performance and power analysis and debug

Help develop and/or evaluate design and verification methodologies and participate in improving existing ones

Collaborate with and provide guidance to the post silicon and software teams for prototype bring up and performance tuning

Provide mentorship to the more junior team members

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What We're Looking For

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 12-18 years of related professional experience.

Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 8-10 years of experience.

Experience in creating architectural, micro-architectural, and register specifications.

Verilog/System Verilog RTL coding with System Verilog assertions

Well-versed in all stages of the ASIC design flow (including specification, architecture and design implementation, prototype bring-up)

Expertise in high speed memory protocols (PCIe Gen4/5/6, CXL 2.0/3.1)

Has worked on complex chips such as network processors, CPUs,GPUs,NOCs,Switches, Machine Learning SoCs etc. owning full chip, subsystem and block level architecture and design

Expertise in any of the following domains would be a big plus: networking, embedded systems architecture, computer architecture, machine learning accelerators

Experience with scripting in Perl/Python/Shell

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Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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