SerDes Principle Analog Design Engineer

The AMSCC-ARF team is part of NXP’s Central Technology Organization's Analog Mixed Signal Competence Center (CTO-AMSCC). AMSCC-ARF employs about 120+ specialists located in Eindhoven, Bangalore, Delft, Kista and Noida with strong focus and competence in developing state-of-the-art Data Converter, Reference, Power Management, RF and mm-Wave IPs that support all NXP Business Lines. AMSCC-ARF team specializes in architecting, designing, and delivering analog and mixed-signal building blocks that are at the heart of competitive NXP products.

Continuing on it’s growth trajectory, fueled by decades of success stories and execution excellence, AMSIP is expanding into developing High Speed Serial Link (HSL) PHYs to support ever growing need of SERDES PHYs by NXP’s Automotive and non-Automotive product lines.

As the HSL Design engineer you will be responsible for performing design feasibility of Tx/Rx/Clocking sub-systems in close coordination with Design Leads and hands-on execution of designs to meet performance, quality and cost targets within the agreed timelines while keeping all stake holders well informed on the progress, challenges, issues and risks.

Responsibilities Include

Working with the design team in defining and completing feasibility analysis of the respective sub-system Tx/Rx/Clocking

End to end ownership of design execution and verification using appropriate views and tools

Documentation of design and presenting reviews to peers and internal customers

Provide innovative technical solutions to address design challenges leading to continuous improvement of various design blocks and sub-systems

Hands-on lab characterization/validation, yield improvement and optimization

Candidate Profile

Master’s/Bachelor’s Degree in Electrical/Electronic engineering from a reputed, tier 1 university with an emphasis in VLSI/IC design

10+ years of extensive experience in design and development of analog/mixed-signal IPs in 40nm or lower geometry CMOS and/or high speed BiCMOS nodes with 4+ years of experience in designing high speed SerDes PHY Tx, Rx and/or Clocking sub-systems in multi Gbps range

Hands-on design experience in designing one or more SerDes blocks like Tx Driver, RX CTLE, Termination, DFE, Signal Detector for NRZ/PAM-4 SerDes PHY is a must

Strong in Analog building blocks design with focus on high-speed design with optimal area and power trade-offs is key to be successful in this role

Good understanding of SerDes development life cycle and experience of multiple SerDes PHY tape-outs and successful silicon bring up is a plus

Good understanding and familiarity with matching, s-parameter, noise/jitter modelling and simulations is desirable

Exposure to automotive design and quality processes is a plus

Experience in automotive/non-automotive ethernet PHY design and development is a plus

Good exposure and strong skills in equalization, bandwidth and linearity improvement techniques is a big plus

SerDes system level understanding and modelling of high speed transceivers is a plus

Ability to work with a creative and innovative mind set both individually as well as in a team

Able to build a network with professionals extending beyond IC design (DfX, Technology, Research, etc.)

Ability to lead a small design team and making technical judgments is a plus

Having significant Technical Publications, patents is a big plus

More information about NXP in India...

R-10055807